infrared_receive.vhd

接收解码用VHDL语言编写程序

---------------------------------------顶层程序-----------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity infrared_receive is
  port(clk,infrared_in: in std_logic;
       key_in: in std_logic_vector(3 downto 0);
       ringout,ledout: out std_logic;
       light: out std_logic_vector(1 downto 0);
       data_result: out std_logic_vector(3 downto 0);
       user_num: out std_logic_vector(2 downto 0));
end infrared_receive;

architecture behav of infrared_receive is
  signal clr: std_logic;
  signal data: std_logic_vector(11 downto 0);
  signal dataout,key_out: std_logic_vector(7 downto 0);
  signal red_ring,red_led,key_ring,key_led: std_logic;
  signal key_first: std_logic; 

  component check is
     Port(clk,infrared_in:in std_logic;
       clr:out std_logic);
  end component;

  component  coding  is
     port(clk,infrared_in,clr: in std_logic;
          data: out std_logic_vector(11 downto 0);
          user_num: out std_logic_vector(2 downto 0);
          red_ring: out std_logic);  
  end component;

  component decode is
     port(clk: in std_logic;
          data: in std_logic_vector(11 downto 0);
          data_out: out std_logic_vector(7 downto 0);
          red_led: out std_logic);
  end component;

  component display is
     port(clk,key_first,infrared_in: in std_logic;
          data_out: in std_logic_vector(7 downto 0);
          key_out: in std_logic_vector(7 downto 0);
          data_result: out std_logic_vector(3 downto 0);
          light: out std_logic_vector(1 downto 0));
  end component;

  component ring_led is
     port(clk,red_ring,key_ring,red_led,key_led: in std_logic;
          ringout,ledout: out std_logic);
  end component;

  component keyboard is
     port(clk: in std_logic;
       key_in: in std_logic_vector(3 downto 0);
       key_out: out std_logic_vector(7 downto 0);
       key_first,key_ring,key_led: out std_logic);
  end component;

  begin
    u1:check port map(clk,infrared_in,clr);
    u2:coding port map(clk,infrared_in,clr,data,user_num,red_ring);
    u3:decode port map(clk,data,dataout,red_led);	
    u4:display port map(clk,key_first,infrared_in,dataout,key_out,data_result,light); 
    u5:ring_led port map(clk,red_ring,key_ring,red_led,key_led,ringout,ledout);
    u6:keyboard port map(clk,key_in,key_out,key_first,key_ring,key_led);
end behav;

-----------------------------------1:检测----------------------------------------
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;             --要用到'+'运算,故包含此程序包

Entity check is
  Port(clk,infrared_in:in std_logic;
       clr:out std_logic);
End check;

Architecture behav of check is
  Type states is(T0,T1);
  Signal state:states;
  Signal cnt:std_logic_vector(4 downto 0);   --用于高电平计数
  Begin
    Process(infrared_in,clk)
      Begin
        if (clk'event and clk='1')then
      Case state is
        when T0=>                            
             clr<='0';
             cnt<="00000";
             if(infrared_in='1') then
             	state<=T1;
             else
             	state<=T0;
             end if;
        when T1=>
             cnt<=cnt+1;                     --如果高电平个数持续16个时钟周期
             if(infrared_in='1') then        --就产生一个清零信号clr
             	if(cnt="10000") then         --使12位寄存器清零
               	 	clr<='1';
                	state<=T0;
             	else state<=T1;
             	end if;
             else state<=T0;
             end if;
        End Case;
      End if;
    End process;
End behav;


-----------------------------------2：编码---------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity coding is
   port(clk,infrared_in,clr: in std_logic;
        data: out std_logic_vector(11 downto 0);
        user_num: out std_logic_vector(2 downto 0);
        red_ring: out std_logic);
end coding;

architecture behav of coding is
type states is(T0,T1,T2,T3,T4,T5);
signal state: states;
signal datareg12: std_logic_vector(11 downto 0);
signal cnt1: std_logic_vector(3 downto 0);   --用于低电平计数
signal cnt2: std_logic_vector(3 downto 0);   --用于接收红外编码位数计数
begin
  process(clk,infrared_in,clr)
  begin
    if(clr='1') then                         
       data<="000000000000";                 --如有clr='1',则编码输出全为0
       state<=T0;
    elsif(clk'event and clk='1') then
       case state is
         when T0=>                           --开始状态
           datareg12<="000000000000";
           cnt1<="0000";
           cnt2<="0000";
           red_ring<='0';           
           if(infrared_in='0') then          --有信号输入,跳到T1状态
              state<=T1;
           else 
              state<=T0;                     --没有信号输入则状态不变
           end if;
         when T1=>
           cnt1<=cnt1+1;
           if(infrared_in='1') then          --红外输入变为高电平结束计数
              if(cnt1>=8) then               --判断0和1
                 state<=T3;  
              else
                 state<=T2;
              end if;
           else
              state<=T1;
           end if;
         when T2=>
           cnt2<=cnt2+1;
           datareg12<=datareg12(10 downto 0)&'0';  --接收的是0
           if(cnt2=11) then
              state<=T4;
           else
              state<=T5;
           end if;
         when T3=>
           cnt2<=cnt2+1;
           datareg12<=datareg12(10 downto 0)&'1';　--接收的是1
           if(cnt2=11) then                        --判断是否接收完12位数据
              state<=T4;
           else
              state<=T5;
           end if;
         when T4=>
           data<=datareg12(11 downto 0);           --输出数据
           user_num<=datareg12(11 downto 9) xor "111";   --显示用户码
           red_ring<='1';                          --响铃
           state<=T0;
         when T5 =>                   --没有接收完12位数据，cnt1清零准备接收
           cnt1<="0000";              --下一位数据,如有数据输入跳到T1状态
           datareg12<=datareg12;
           if(infrared_in='1') then
              state<=T5;
           else
              state<=T1;
           end if;
       end case;
     end if;
  end process;
end behav;  

-----------------------------------3：解码---------------------------------------
library ieee;
use ieee.std_logic_1164.all;

entity decode is
  port(clk: in std_logic;
       data: in std_logic_vector(11 downto 0);
       data_out: out std_logic_vector(7 downto 0);
       red_led: out std_logic);
end decode;

architecture rtl of decode is
  signal bcd_code: std_logic_vector(7 downto 0);
  signal led_reg: std_logic;

begin
  process(clk)
   begin
     if(clk'event and clk='1') then
        case data is
           when "111100100000" =>bcd_code<="00000001"; led_reg<='0'; --接收1，以此类推至18
           when "111100010000" =>bcd_code<="00000010"; led_reg<='0';       
           when "111100001000" =>bcd_code<="00000011"; led_reg<='0';
           when "111100000100" =>bcd_code<="00000100"; led_reg<='0';
           when "111100000010" =>bcd_code<="00000101"; led_reg<='0';
           when "111100000001" =>bcd_code<="00000110"; led_reg<='0';

           when "111010100000" =>bcd_code<="00000111"; led_reg<='1'; --接收7
           when "111010010000" =>bcd_code<="00001000"; led_reg<='1';
           when "111010001000" =>bcd_code<="00001001"; led_reg<='1';
           when "111010000100" =>bcd_code<="00010000"; led_reg<='1';
           when "111010000010" =>bcd_code<="00010001"; led_reg<='1';
           when "111010000001" =>bcd_code<="00010010"; led_reg<='1';

           when "111001100000" =>bcd_code<="00010011"; led_reg<='1'; --接收13
           when "111001010000" =>bcd_code<="00010100"; led_reg<='1';
           when "111001001000" =>bcd_code<="00010101"; led_reg<='1';
           when "111001000100" =>bcd_code<="00010110"; led_reg<='1';
           when "111001000010" =>bcd_code<="00010111"; led_reg<='1';
           when "111001000001" =>bcd_code<="00011000"; led_reg<='1';
           when others =>bcd_code<=null; led_reg<='1';
        end case;
     end if;
  end process;
  data_out<=bcd_code(7 downto 0);  --输出8位BCD码
  red_led<=led_reg;　　　　　　　　--输出亮灯信号
end rtl;

-----------------------------------4：数码显示---------------------------------------
library ieee;
use ieee.std_logic_1164.all;

entity display is
  port(clk,key_first,infrared_in: in std_logic;
       data_out: in std_logic_vector(7 downto 0);
       key_out: in std_logic_vector(7 downto 0);
       data_result: out std_logic_vector(3 downto 0);
       light: out std_logic_vector(1 downto 0));
end display;

architecture behav of display is
  signal cnt4: integer range 0 to 2;         --用于循环显示计数
  signal data8: std_logic_vector(7 downto 0);--当前要显示的8位BCD码
begin
  p1: process(clk,key_first,infrared_in,key_out) is
    begin
      if(key_first='1') then                 --键盘优先显示　
         data8<=key_out(7 downto 0);         
      elsif(clk'event and clk='1') then
         if(infrared_in='1') then
         data8<=data_out(7 downto 0);
         end if;
      end if; 
  end process p1; 

  p2: process(clk,cnt4,data8) is
    begin
      if(clk'event and clk='1') then
         if(cnt4=0) then 
            data_result<=data8(7 downto 4);  --显示十位
            light<="10";
            cnt4<=cnt4+1;
         elsif(cnt4=1) then
            data_result<=data8(3 downto 0);　--显示个位
            light<="01";
            cnt4<=cnt4+1;
         elsif(cnt4=2) then
            cnt4<=0;                         --回到初状态为显示下一个
         end if;                             --数据作准备
      end if;      
  end process p2;  
end behav;  

------------------------------------5:响铃及亮灯-----------------------------------
library ieee;
use ieee.std_logic_1164.all;

entity ring_led is
  port(clk,red_ring,key_ring,red_led,key_led: in std_logic;
       ringout,ledout: out std_logic);
end ring_led;

architecture behav of ring_led is
type states is(T0,T1);
signal state: states;
signal ledout_reg,ringout_reg: std_logic;
begin
  process(clk,red_ring,red_led)
  variable cnt3: integer range 0 to 50;    --用于延时计数
  begin
    if(clk'event and clk='1') then
       case state is
         when T0=>                         --不响铃，不亮灯状态
           ringout_reg<='0';
           cnt3:=0;
           ledout_reg<='1';
           if(red_ring='1') then           
              state<=T1;
           else
              state<=T0;
           end if;
         when T1=>                         --响铃和亮灯状态
           ringout_reg<='1';
           if(red_led='0') then
              ledout_reg<='0';
           end if;
           cnt3:=cnt3+1;
           if(cnt3=49) then                --判断延时是否结束
              state<=T0;
           else
              state<=T1;
           end if;
       end case;
     end if;
   end process;
   ringout<=ringout_reg or key_ring;       --响铃输出
   ledout<=ledout_reg and key_led;         --亮灯输出
end behav;

---------------------------------6:键盘输入---------------------------------------
library ieee;
use ieee.std_logic_1164.all;

entity keyboard is
  port(clk: in std_logic;
       key_in: in std_logic_vector(3 downto 0);
       key_out: out std_logic_vector(7 downto 0);
       key_first,key_ring,key_led: out std_logic);
end keyboard;

architecture rtl of keyboard is
  signal key_bcd: std_logic_vector(7 downto 0);
  signal key_H: std_logic;
  signal key_ring_reg: std_logic;
  signal key_led_reg: std_logic;  
begin
  process(clk,key_in)
    begin
      if(clk'event and clk='1') then
         case key_in is
           when "0111" =>               --按键是1
                key_bcd<="00000001"; 　 --输出1的BCD码
                key_H<='1';　　　　　　 --键盘优先标志
                key_ring_reg<='1';      --响铃
                key_led_reg<='0';       --亮灯
           when "1011" =>
                key_bcd<="00000010";    --按键是2
                key_H<='1';  
                key_ring_reg<='1'; 
                key_led_reg<='0';        
           when "1101" =>
                key_bcd<="00000011";    --按键是3
                key_H<='1';
                key_ring_reg<='1'; 
                key_led_reg<='0';
           when "1110" =>
                key_bcd<="00000100";    --按键是4
                key_H<='1';
                key_ring_reg<='1';
                key_led_reg<='0';
           when others =>      
                key_bcd<=null;          --其它状态，输出0且不响铃，不亮灯
                key_H<='0';
                key_ring_reg<='0'; 
                key_led_reg<='1';
         end case;
      end if;
  end process;
  key_out<=key_bcd(7 downto 0);   --输出要显示的BCD码
  key_first<=key_H;
  key_ring<=key_ring_reg; 
  key_led<=key_led_reg;
end rtl;