infrared_receive.map.rpt

接收解码用VHDL语言编写程序

Analysis & Synthesis report for infrared_receive
Sat May 24 16:49:43 2008
Version 4.0 Build 190 1/28/2004 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Default Parameter Settings
  5. Analysis & Synthesis Files Read
  6. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2004 Altera Corporation
Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
support information,  device programming or simulation file,  and any other
associated  documentation or information  provided by  Altera  or a partner
under  Altera's   Megafunction   Partnership   Program  may  be  used  only
to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
other  use  of such  megafunction  design,  netlist,  support  information,
device programming or simulation file,  or any other  related documentation
or information  is prohibited  for  any  other purpose,  including, but not
limited to  modification,  reverse engineering,  de-compiling, or use  with
any other  silicon devices,  unless such use is  explicitly  licensed under
a separate agreement with  Altera  or a megafunction partner.  Title to the
intellectual property,  including patents,  copyrights,  trademarks,  trade
secrets,  or maskworks,  embodied in any such megafunction design, netlist,
support  information,  device programming or simulation file,  or any other
related documentation or information provided by  Altera  or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.



+-----------------------------------------------------------------+
; Analysis & Synthesis Summary                                    ;
+-----------------------------+-----------------------------------+
; Analysis & Synthesis Status ; Failed - Sat May 24 16:49:43 2008 ;
; Revision Name               ; infrared_receive                  ;
; Top-level Entity Name       ; infrared_receive                  ;
; Family                      ; Stratix                           ;
+-----------------------------+-----------------------------------+


+--------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                              ;
+---------------------------------------------------------------------------------------------
; Option                                                  ; Setting          ; Default Value ;
+---------------------------------------------------------+------------------+---------------+
; Top-level entity name                                   ; infrared_receive ;               ;
; Auto Resource Sharing                                   ; Off              ; Off           ;
; Auto RAM Block Balancing                                ; On               ; On            ;
; Auto Shift Register Replacement                         ; On               ; On            ;
; Auto DSP Block Replacement                              ; On               ; On            ;
; Auto RAM Replacement                                    ; On               ; On            ;
; Auto ROM Replacement                                    ; On               ; On            ;
; Allow register retiming to trade off Tsu/Tco with Fmax  ; On               ; On            ;
; Perform gate-level register retiming                    ; Off              ; Off           ;
; Perform WYSIWYG Primitive Resynthesis                   ; Off              ; Off           ;
; Remove Duplicate Logic                                  ; On               ; On            ;
; Auto Open-Drain Pins                                    ; On               ; On            ;
; Auto Carry Chains                                       ; On               ; On            ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II ; 70               ; 70            ;
; Optimization Technique -- Stratix/Stratix GX            ; Balanced         ; Balanced      ;
; Auto Global Register Control Signals                    ; On               ; On            ;
; Auto Global Clock                                       ; On               ; On            ;
; Limit AHDL Integers to 32 Bits                          ; Off              ; Off           ;
; Ignore SOFT Buffers                                     ; On               ; On            ;
; Ignore LCELL Buffers                                    ; Off              ; Off           ;
; Ignore ROW GLOBAL Buffers                               ; Off              ; Off           ;
; Ignore GLOBAL Buffers                                   ; Off              ; Off           ;
; Ignore CASCADE Buffers                                  ; Off              ; Off           ;
; Ignore CARRY Buffers                                    ; Off              ; Off           ;
; Remove Duplicate Registers                              ; On               ; On            ;
; Remove Redundant Logic Cells                            ; Off              ; Off           ;
; Power-Up Don't Care                                     ; On               ; On            ;
; NOT Gate Push-Back                                      ; On               ; On            ;
; DSP Block Balancing                                     ; Auto             ; Auto          ;
; State Machine Processing                                ; Auto             ; Auto          ;
; Family name                                             ; Stratix          ; Stratix       ;
; VHDL Version                                            ; VHDL93           ; VHDL93        ;
; Verilog Version                                         ; Verilog_2001     ; Verilog_2001  ;
; Preserve fewer node names                               ; On               ; On            ;
; Disk space/compilation speed tradeoff                   ; Normal           ; Normal        ;
; Create Debugging Nodes for IP Cores                     ; off              ; off           ;
+---------------------------------------------------------+------------------+---------------+


+-------------------------------------------------+
; Analysis & Synthesis Default Parameter Settings ;
+--------------------------------------------------
; Name               ; Setting                    ;
+--------------------+----------------------------+
; CARRY_CHAIN        ; MANUAL                     ;
; CASCADE_CHAIN      ; MANUAL                     ;
; OPTIMIZE_FOR_SPEED ; 5                          ;
; STYLE              ; FAST                       ;
+--------------------+----------------------------+


+---------------------------------+
; Analysis & Synthesis Files Read ;
+----------------------------------
; File Name ; Read                ;
+-----------+---------------------+


+--------------------------------+
; Analysis & Synthesis Messages  ;
+--------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.0 Build 190 1/28/2004 SJ Full Version
    Info: Processing started: Sat May 24 16:49:42 2008
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off infrared_receive -c infrared_receive
Error: VHDL syntax error at infrared_receive.vhd(170) near text ?
Error: VHDL syntax error at infrared_receive.vhd(170) near text "?; expecting "loop"
Error: Ignored construct behav at infrared_receive.vhd(125) because of previous errors
Error: Ignored construct decode at infrared_receive.vhd(198) because of previous errors
Error: VHDL error at infrared_receive.vhd(205): entity decode is used but not declared
Error: VHDL error at infrared_receive.vhd(206): object std_logic_vector is used but not declared
Error: VHDL error at infrared_receive.vhd(207): object std_logic is used but not declared
Error: VHDL error at infrared_receive.vhd(214): object bcd_code is used but not declared
Error: VHDL error at infrared_receive.vhd(214): object led_reg is used but not declared
Error: VHDL error at infrared_receive.vhd(215): object bcd_code is used but not declared
Error: VHDL error at infrared_receive.vhd(215): object led_reg is used but not declared
Error: VHDL error at infrared_receive.vhd(216): object bcd_code is used but not declared
Error: VHDL error at infrared_receive.vhd(216): object led_reg is used but not declared
Error: VHDL error at infrared_receive.vhd(217): object bcd_code is used but not declared
Error: VHDL error at infrared_receive.vhd(217): object led_reg is used but not declared
Error: VHDL error at infrared_receive.vhd(218): object bcd_code is used but not declared
Error: VHDL error at infrared_receive.vhd(218): object led_reg is used but not declared
Error: VHDL error at infrared_receive.vhd(219): object bcd_code is used but not declared
Error: VHDL error at infrared_receive.vhd(219): object led_reg is used but not declared
Info: Found 0 design units and 0 entities in source file infrared_receive.vhd
Error: Quartus II Analysis & Synthesis was unsuccessful. 19 errors, 0 warnings
    Error: Processing ended: Sat May 24 16:49:43 2008
    Error: Elapsed time: 00:00:01