timespace_insert.vhd

本代码用于在两个数据报文之间插入一个周期的时钟间隔

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
--------------
--功能：在连续的包文间插入两个时钟周期间隔，便于后续b口封装模块插入两个周期的内部包头。
--说明：afifo135x128的深度可以不受限制，但由于出口带宽小入口带宽，设输入包间间隔为一个时钟周期，平均包长为N则输出带宽为输入带宽的(N/16-1)/(N/16)=(1-16/N)，因此需在入端加入丢包处理。
entity timespace_insert is
	port
	(
		reset : in std_logic;
		gclk : in std_logic;
		
		sop_in : in std_logic;
		eop_in : in std_logic;
		rval_in : in std_logic;
		data_in : in std_logic_vector(127 downto 0);
		size_in : in std_logic_vector(3 downto 0);
		
		sop_out : out std_logic;
		eop_out : out std_logic;
		rval_out : out std_logic;
		data_out : out std_logic_vector(127 downto 0);
		size_out : out std_logic_vector(3 downto 0)
	);
end timespace_insert;

architecture a of timespace_insert is

component afifo135x128
	port (
		din	 : in std_logic_vector(134 downto 0);
		clk	 : in std_logic;
		rd_en	 : in std_logic;
		rst	 : in std_logic;
		wr_en	 : in std_logic;
		dout	 	 : out std_logic_vector(134 downto 0);
		empty : out std_logic;
		full : out std_logic;
		prog_full : out std_logic --利用预置值进行丢包判断，目前为100word，fifo使用深度超过100时，不再写入

		);
end component;


signal fifo_rd_en,fifo_rd_begin,fifo_rd_en_d1,fifo_rd_en_d2 : std_logic;
signal fifo_wr_en,fifo_empty,fifo_pro_full,fifo_wr_allow : std_logic;
signal soptoeop,sop_in_d1,eop_in_d1,rval_in_d1: std_logic;
signal fifo_din,fifo_dout : std_logic_vector(134 downto 0);
signal size_in_d1 : std_logic_vector(3 downto 0);
signal data_in_d1: std_logic_vector(127 downto 0);


begin

process(reset,gclk)

begin
	if reset='1' then
		sop_in_d1 <='0';
		eop_in_d1 <='0';
		rval_in_d1 <='0';
		data_in_d1 <=(others=>'0');
		size_in_d1 <=(others=>'0');
	elsif gclk='1' and gclk'event then
		sop_in_d1 <=sop_in;
		eop_in_d1 <=eop_in;
		rval_in_d1 <=rval_in;
		data_in_d1 <=data_in;
		size_in_d1 <=size_in;
	end if;
end process;

process(reset,gclk)--头到尾
begin
	if reset='1' then
	fifo_wr_allow <= '0';
	elsif gclk='1' and gclk'event then
		if sop_in='1' and fifo_pro_full ='0' then
			fifo_wr_allow <= '1';
		elsif sop_in='1' and fifo_pro_full ='1' then
			fifo_wr_allow <= '0';
		end if;
	end if;
end process;

fifo_din<=rval_in_d1 & size_in_d1 & eop_in_d1 & sop_in_d1 & data_in_d1;
fifo_wr_en<=rval_in_d1 and fifo_wr_allow;

----latch the information of this board
process(reset,gclk)
begin
	if reset='1' then
		fifo_rd_en_d1 <='0';
		fifo_rd_en_d2 <='0';
	elsif gclk='1' and gclk'event then
		fifo_rd_en_d1<=fifo_rd_en;
		fifo_rd_en_d2<=fifo_rd_en_d1;
	end if;
end process;

process(reset,gclk)
begin
	if reset='1' then
		fifo_rd_begin <='0';
	elsif gclk='1' and gclk'event then
		if (fifo_rd_en_d1='0' and fifo_empty='0') then --fifo不空，且与上一次读后插入给定间隔后，则开始读
			fifo_rd_begin <= '1';
		elsif (fifo_rd_en_d1='1' and fifo_dout(129)='1') then
			fifo_rd_begin <= '0';			
		end if;
	end if;
end process;

fifo_rd_en<=fifo_rd_begin and (not (fifo_rd_en_d1 and fifo_dout(129))); --开始读直到读到包尾则停止读

fifo : afifo135x128 PORT MAP (
		din	 => fifo_din,
		clk	 => gclk,
		rd_en	 => fifo_rd_en,
		rst	 => reset,
		wr_en	 => fifo_wr_en,
		empty =>fifo_empty,
		dout	 	 => fifo_dout,
		full => fifo_pro_full
	); 

sop_out<=fifo_rd_en_d1 and fifo_dout(128);
eop_out<=fifo_rd_en_d1 and fifo_dout(129);
rval_out<=fifo_rd_en_d1 and fifo_dout(134);
size_out<=fifo_dout(133 downto 130);
data_out<=fifo_dout(127 downto 0);

end a;