combine_module.vhd

本代码根据包头、包尾指示

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    07:58:53 09/27/2007 
-- Design Name: 
-- Module Name:    up_combine_module - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
-- 本模块完成将两路数据合为一路数据输出的功能
--                  --by 杨琴

-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity combine_module is
port(
			reset			:	in std_logic;
			clk125		:	in std_logic;
			           	
			data1_in	:	in std_logic_vector(129 downto 0);
			data2_in	:	in std_logic_vector(129 downto 0);
			data_out	:	out std_logic_vector(129 downto 0)
		);
end combine_module;

architecture Behavioral of combine_module is

component data_fifo130x512
port(
			rst					:	in std_logic;
			clk					:	in std_logic;
			wr_en				:	in std_logic;
			rd_en				:	in std_logic;
			din					:	in std_logic_vector(129 downto 0);
			dout				:	out std_logic_vector(129 downto 0);
			full				:	out std_logic;
			prog_full		:	out std_logic;
			empty				:	out std_logic
		);
end component;

component flag_fifo1x128
	port (
	clk					: 	IN std_logic;
	din					: 	IN std_logic_VECTOR(0 downto 0);
	rd_en				: 	IN std_logic;
	rst					: 	IN std_logic;
	wr_en				: 	IN std_logic;
	dout				: 	OUT std_logic_VECTOR(0 downto 0);
	empty				: 	OUT std_logic;
	full				: 	OUT std_logic);
end component;
			

signal data1_in_d1,data1_in_d2 : std_logic_vector(129 downto 0);
signal data1_wr_en : std_logic;
signal data1_rd_en_temp,data1_rd_en,data1_rd_en_d1 : std_logic;
signal mux1,data1_out : std_logic_vector(129 downto 0);
signal eop1_true : std_logic;
signal data1_full,data1_prog_full : std_logic;
signal data1_empty : std_logic;
signal flag1_wr_en : std_logic;
signal flag1_rd_en : std_logic;
signal flag1_empty : std_logic;
signal sel1 : std_logic;

signal data2_in_d1,data2_in_d2 : std_logic_vector(129 downto 0);
signal data2_wr_en : std_logic;
signal data2_rd_en_temp,data2_rd_en,data2_rd_en_d1 : std_logic;
signal mux2,data2_out : std_logic_vector(129 downto 0);
signal eop2_true : std_logic;
signal data2_full,data2_prog_full : std_logic;
signal data2_empty : std_logic;
signal flag2_wr_en : std_logic;
signal flag2_rd_en : std_logic;
signal flag2_empty : std_logic;

signal mux : std_logic_vector(129 downto 0);
signal sel : std_logic_vector(1 downto 0);



begin

----******************************************
----			数据通路1写入fifo
----******************************************

process(reset,clk125)
begin
	if reset='1' then
		data1_in_d1 <= (others => '0');
		data1_in_d2 <= (others => '0');
	elsif clk125='1' and clk125'event then
		data1_in_d1 <= data1_in;
		data1_in_d2 <= data1_in_d1;
	end if;
end process;

----通路1的数据fifo写使能信号

process(reset,clk125)
begin
	if reset='1' then
		data1_wr_en <= '0';
	elsif clk125='1' and clk125'event then
		if data1_in_d1(129)='1' and data1_prog_full='0' then
			data1_wr_en <='1';
		elsif data1_in_d2(128)='1' then
			data1_wr_en <= '0';
		end if;
	end if;
end  process;


----通路1的数据fifo读使能信号

process(reset,clk125)
begin
	if reset='1' then
		data1_rd_en_temp <= '0';
	elsif clk125='1' and clk125'event then
		if flag1_empty='0' then
			data1_rd_en_temp <= '1';
		elsif eop1_true='1' then
			data1_rd_en_temp <= '0';
		end if;
	end if;
end process;

process(reset,clk125)
begin
	if reset='1' then
		mux1 <= (others => '0');
	elsif clk125='1' and clk125'event then
		if data1_rd_en='1' then
			mux1 <= data1_out;
		else
			mux1 <= (others => '0');
		end if;
	end if;
end process;

eop1_true <= mux1(128) and data1_rd_en_d1;

data1_rd_en <= data1_rd_en_temp and (not eop1_true) and sel1;

process(reset,clk125)
begin
	if reset='1' then
		data1_rd_en_d1 <= '0';
	elsif clk125='1' and clk125'event then
		data1_rd_en_d1 <= data1_rd_en;
	end if;
end process;


----通路1的标志fifo的读/写使能信号

flag1_wr_en <= data1_in_d2(128) and data1_wr_en;

flag1_rd_en <= data1_rd_en and (not data1_rd_en_d1);


data1_fifo : data_fifo130x512 port map
(
	rst					=>	reset,
	clk					=>	clk125,
	wr_en				=>	data1_wr_en,
	rd_en				=>	data1_rd_en,
	din					=>	data1_in_d2,
	dout				=>	data1_out,
	full				=>	data1_full,
	prog_full		=>	data1_prog_full,
	empty				=>	data1_empty
);

flag1_fifo : flag_fifo1x128 port map
(
	rst					=>	reset,
	clk					=>	clk125,
	wr_en				=>	flag1_wr_en,
	rd_en				=>	flag1_rd_en,
	din					=>	"1",
	dout				=>	open,
	empty				=>	flag1_empty
);



----********************************************
----				数据通路2写入fifo
----********************************************

process(reset,clk125)
begin
	if reset='1' then
		data2_in_d1 <= (others => '0');
		data2_in_d2 <= (others => '0');
	elsif clk125='1' and clk125'event then
		data2_in_d1 <= data2_in;
		data2_in_d2 <= data2_in_d1;
	end if;
end process;

process(reset,clk125)
begin
	if reset='1' then
		data2_wr_en <= '0';
	elsif clk125='1' and clk125'event then
		if data2_in_d1(129)='1' and data2_prog_full='0' then
			data2_wr_en <= '1';
		elsif data2_in_d2(128)='1' then
			data2_wr_en <= '0';
		end if;
	end if;
end process;

process(reset,clk125)
begin
	if reset='1' then
		data2_rd_en_temp <= '0';
	elsif clk125='1' and clk125'event then
		if flag2_empty='0' then
			data2_rd_en_temp <= '1';
		elsif eop2_true='1' then
			data2_rd_en_temp <= '0';
		end if;
	end if;
end process;

process(reset,clk125)
begin
	if reset='1' then
		mux2 <= (others => '0');
	elsif clk125='1' and clk125'event then
		if data2_rd_en='1' then
			mux2 <= data2_out;
		else
			mux2 <= (others => '0');
		end if;
	end if;
end process;

eop2_true <= mux2(128) and data2_rd_en_d1;

data2_rd_en <= data2_rd_en_temp and (not eop2_true) and (not sel1);

process(reset,clk125)
begin
	if reset='1' then
		data2_rd_en_d1 <= '0';
	elsif clk125='1' and clk125'event then
		data2_rd_en_d1 <= data2_rd_en;
	end if;
end process;


----通路2的标志fifo的读/写使能信号

flag2_wr_en <= data2_in_d2(128) and data2_wr_en;

flag2_rd_en <= data2_rd_en and (not data2_rd_en_d1);


data2_fifo : data_fifo130x512 port map
(
	rst					=>	reset,
	clk					=>	clk125,
	wr_en				=>	data2_wr_en,
	rd_en				=>	data2_rd_en,
	din					=>	data2_in_d2,
	dout				=>	data2_out,
	full				=>	data2_full,
	prog_full		=>	data2_prog_full,
	empty				=>	data2_empty
);

flag2_fifo : flag_fifo1x128 port map
(
	rst					=>	reset,
	clk					=>	clk125,
	wr_en				=>	flag2_wr_en,
	rd_en				=>	flag2_rd_en,
	din					=>	"1",
	dout				=>	open,
	empty				=>	flag2_empty
);



----********************************************
----			选择通路1/2输出
----********************************************

process(reset,clk125)
begin
	if reset='1' then
		sel1 <= '0';
	elsif clk125='1' and clk125'event then
		if data1_rd_en='1' then
			sel1 <= '1';
		elsif data2_rd_en='1' then
			sel1 <= '0';
		else
			sel1 <= not sel1;
		end if;
	end if;
end process;

sel <= data1_rd_en_d1 & data2_rd_en_d1;

process(reset,clk125)
begin
	if reset='1' then
		mux <= (others => '0');
	elsif clk125='1' and clk125'event then
		case sel is 
			when "10" => mux <= mux1;
			when "01" => mux <= mux2;
			when "00" => mux <= (others => '0');
			when "11" => mux <= (others => '0');
			when others => NULL;
		end case;
	end if;
end process;

data_out <= mux;



end Behavioral;