selects.rpt

米字型数码管的编码方法。自动循环显示至少四个以上单词。

 sele0   = DFFE( _EQ040 $  data0, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ040 = !data0 & !data1 & !data2 & !data3 &  sele0;

-- Node name is 'sele1' = ':70' 
-- Equation name is 'sele1', type is output 
 sele1   = DFFE( _EQ041 $  data1, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ041 = !data0 & !data1 & !data2 & !data3 &  sele1;

-- Node name is 'sele2' = ':68' 
-- Equation name is 'sele2', type is output 
 sele2   = DFFE( _EQ042 $  data2, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ042 = !data0 & !data1 & !data2 & !data3 &  sele2;

-- Node name is 'sele3' = ':66' 
-- Equation name is 'sele3', type is output 
 sele3   = DFFE( _EQ043 $  data3, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ043 = !data0 & !data1 & !data2 & !data3 &  sele3;

-- Node name is '|LPM_ADD_SUB:1084|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC047', type is buried 
_LC047   = LCELL( cont3 $  _EQ044);
  _EQ044 = !cont0 & !cont1 & !cont2;

-- Node name is '~1354~1' 
-- Equation name is '~1354~1', location is LC053, type is buried.
-- synthesized logic cell 
_LC053   = LCELL( _EQ045 $  GND);
  _EQ045 = !num1 & !outp15 & !X115 & !X215
         # !num0 & !outp15 & !X115 & !X315
         #  cont0 & !outp15
         #  cont1 & !outp15
         #  cont2 & !outp15;

-- Node name is '~1360~1' 
-- Equation name is '~1360~1', location is LC046, type is buried.
-- synthesized logic cell 
_LC046   = LCELL( _EQ046 $  GND);
  _EQ046 = !num1 & !outp14 & !X114 & !X214
         # !num0 & !outp14 & !X114 & !X314
         #  cont0 & !outp14
         #  cont1 & !outp14
         #  cont2 & !outp14;

-- Node name is '~1366~1' 
-- Equation name is '~1366~1', location is LC018, type is buried.
-- synthesized logic cell 
_LC018   = LCELL( _EQ047 $  GND);
  _EQ047 = !num1 & !outp13 & !X113 & !X213
         # !num0 & !outp13 & !X113 & !X313
         #  cont0 & !outp13
         #  cont1 & !outp13
         #  cont2 & !outp13;

-- Node name is '~1372~1' 
-- Equation name is '~1372~1', location is LC055, type is buried.
-- synthesized logic cell 
_LC055   = LCELL( _EQ048 $  GND);
  _EQ048 = !num1 & !outp12 & !X112 & !X212
         # !num0 & !outp12 & !X112 & !X312
         #  cont0 & !outp12
         #  cont1 & !outp12
         #  cont2 & !outp12;

-- Node name is '~1378~1' 
-- Equation name is '~1378~1', location is LC092, type is buried.
-- synthesized logic cell 
_LC092   = LCELL( _EQ049 $  GND);
  _EQ049 = !num1 & !outp11 & !X111 & !X211
         # !num0 & !outp11 & !X111 & !X311
         #  cont0 & !outp11
         #  cont1 & !outp11
         #  cont2 & !outp11;

-- Node name is '~1384~1' 
-- Equation name is '~1384~1', location is LC085, type is buried.
-- synthesized logic cell 
_LC085   = LCELL( _EQ050 $  GND);
  _EQ050 = !num1 & !outp10 & !X110 & !X210
         # !num0 & !outp10 & !X110 & !X310
         #  cont0 & !outp10
         #  cont1 & !outp10
         #  cont2 & !outp10;

-- Node name is '~1390~1' 
-- Equation name is '~1390~1', location is LC088, type is buried.
-- synthesized logic cell 
_LC088   = LCELL( _EQ051 $  GND);
  _EQ051 = !num1 & !outp9 & !X19 & !X29
         # !num0 & !outp9 & !X19 & !X39
         #  cont0 & !outp9
         #  cont1 & !outp9
         #  cont2 & !outp9;

-- Node name is '~1396~1' 
-- Equation name is '~1396~1', location is LC094, type is buried.
-- synthesized logic cell 
_LC094   = LCELL( _EQ052 $  GND);
  _EQ052 = !num1 & !outp8 & !X18 & !X28
         # !num0 & !outp8 & !X18 & !X38
         #  cont0 & !outp8
         #  cont1 & !outp8
         #  cont2 & !outp8;

-- Node name is '~1402~1' 
-- Equation name is '~1402~1', location is LC072, type is buried.
-- synthesized logic cell 
_LC072   = LCELL( _EQ053 $  GND);
  _EQ053 = !num1 & !outp7 & !X17 & !X27
         # !num0 & !outp7 & !X17 & !X37
         #  cont0 & !outp7
         #  cont1 & !outp7
         #  cont2 & !outp7;

-- Node name is '~1408~1' 
-- Equation name is '~1408~1', location is LC074, type is buried.
-- synthesized logic cell 
_LC074   = LCELL( _EQ054 $  GND);
  _EQ054 = !num1 & !outp6 & !X16 & !X26
         # !num0 & !outp6 & !X16 & !X36
         #  cont0 & !outp6
         #  cont1 & !outp6
         #  cont2 & !outp6;

-- Node name is '~1414~1' 
-- Equation name is '~1414~1', location is LC076, type is buried.
-- synthesized logic cell 
_LC076   = LCELL( _EQ055 $  GND);
  _EQ055 = !num1 & !outp5 & !X15 & !X25
         # !num0 & !outp5 & !X15 & !X35
         #  cont0 & !outp5
         #  cont1 & !outp5
         #  cont2 & !outp5;

-- Node name is '~1420~1' 
-- Equation name is '~1420~1', location is LC073, type is buried.
-- synthesized logic cell 
_LC073   = LCELL( _EQ056 $  GND);
  _EQ056 = !num1 & !outp4 & !X14 & !X24
         # !num0 & !outp4 & !X14 & !X34
         #  cont0 & !outp4
         #  cont1 & !outp4
         #  cont2 & !outp4;

-- Node name is '~1426~1' 
-- Equation name is '~1426~1', location is LC090, type is buried.
-- synthesized logic cell 
_LC090   = LCELL( _EQ057 $  GND);
  _EQ057 = !num1 & !outp3 & !X13 & !X23
         # !num0 & !outp3 & !X13 & !X33
         #  cont0 & !outp3
         #  cont1 & !outp3
         #  cont2 & !outp3;

-- Node name is '~1432~1' 
-- Equation name is '~1432~1', location is LC043, type is buried.
-- synthesized logic cell 
_LC043   = LCELL( _EQ058 $  GND);
  _EQ058 = !num1 & !outp2 & !X12 & !X22
         # !num0 & !outp2 & !X12 & !X32
         #  cont0 & !outp2
         #  cont1 & !outp2
         #  cont2 & !outp2;

-- Node name is '~1438~1' 
-- Equation name is '~1438~1', location is LC002, type is buried.
-- synthesized logic cell 
_LC002   = LCELL( _EQ059 $  GND);
  _EQ059 = !num1 & !outp1 & !X11 & !X21
         # !num0 & !outp1 & !X11 & !X31
         #  cont0 & !outp1
         #  cont1 & !outp1
         #  cont2 & !outp1;

-- Node name is '~1444~1' 
-- Equation name is '~1444~1', location is LC035, type is buried.
-- synthesized logic cell 
_LC035   = LCELL( _EQ060 $  GND);
  _EQ060 = !num1 & !outp0 & !X10 & !X20
         # !num0 & !outp0 & !X10 & !X30
         #  cont0 & !outp0
         #  cont1 & !outp0
         #  cont2 & !outp0;

-- Node name is '~1444~2' 
-- Equation name is '~1444~2', location is LC038, type is buried.
-- synthesized logic cell 
_LC038   = LCELL( _EQ061 $  GND);
  _EQ061 =  cont3 & !outp0;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                        e:\msmg\selects.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000S' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:01
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:02
   --------------------------             --------
   Total Time                             00:00:03


Memory Allocated
-----------------

Peak memory allocated during compilation  = 16,235K