📄 selects.rpt
字号:
109 (108) (G) INPUT 0 0 0 0 0 1 0 X415
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: e:\msmg\selects.rpt
selects
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
136 126 H FF + t 1 0 1 4 8 0 2 outp0
121 113 H FF + t 2 0 1 4 8 1 1 outp1
101 99 G FF + t 2 0 1 4 8 1 1 outp2
80 81 F FF + t 2 0 1 4 8 1 1 outp3
65 69 E FF + t 2 0 1 4 8 1 1 outp4
64 68 E FF + t 2 0 1 4 8 1 1 outp5
63 67 E FF + t 2 0 1 4 8 1 1 outp6
62 65 E FF + t 2 0 1 4 8 1 1 outp7
93 89 F FF + t 2 0 1 4 8 1 1 outp8
97 93 F FF + t 2 0 1 4 8 1 1 outp9
91 86 F FF + t 2 0 1 4 8 1 1 outp10
110 109 G FF + t 2 0 1 4 8 1 1 outp11
103 101 G FF + t 2 0 1 4 8 1 1 outp12
122 115 H FF + t 2 0 1 4 8 1 1 outp13
59 49 D FF + t 2 0 1 4 8 1 1 outp14
100 97 G FF + t 2 0 1 4 8 1 1 outp15
137 128 H FF + t 0 0 0 0 5 1 0 sele0
58 51 D FF + t 0 0 0 0 5 1 0 sele1
134 124 H FF + t 0 0 0 0 5 1 0 sele2
135 125 H FF + t 0 0 0 0 5 1 0 sele3
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\msmg\selects.rpt
selects
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
- 47 C SOFT t 0 0 0 0 4 0 1 |LPM_ADD_SUB:1084|addcore:adder|addcore:adder0|result_node3
(19) 20 B DFFE + t 0 0 0 0 4 4 4 data3 (:106)
- 34 C DFFE + t 0 0 0 0 4 4 3 data2 (:107)
(15) 24 B DFFE + t 0 0 0 0 4 4 3 data1 (:108)
(12) 28 B DFFE + t 0 0 0 0 1 4 3 data0 (:109)
(41) 33 C DFFE + t 0 0 0 0 5 16 5 cont3 (:110)
- 31 B TFFE + t 0 0 0 0 2 16 20 cont2 (:111)
(28) 41 C TFFE + t 0 0 0 0 1 16 21 cont1 (:112)
(13) 27 B TFFE + t 0 0 0 0 0 16 22 cont0 (:113)
- 42 C TFFE + t 0 0 0 0 5 16 16 num1 (:114)
- 26 B TFFE + t 0 0 0 0 4 16 17 num0 (:115)
(56) 53 D SOFT s t 1 0 1 3 6 1 0 ~1354~1
(23) 46 C SOFT s t 1 0 1 3 6 1 0 ~1360~1
- 18 B SOFT s t 1 0 1 3 6 1 0 ~1366~1
- 55 D SOFT s t 1 0 1 3 6 1 0 ~1372~1
(96) 92 F SOFT s t 1 0 1 3 6 1 0 ~1378~1
(90) 85 F SOFT s t 1 0 1 3 6 1 0 ~1384~1
(92) 88 F SOFT s t 1 0 1 3 6 1 0 ~1390~1
(98) 94 F SOFT s t 1 0 1 3 6 1 0 ~1396~1
(68) 72 E SOFT s t 1 0 1 3 6 1 0 ~1402~1
- 74 E SOFT s t 1 0 1 3 6 1 0 ~1408~1
(71) 76 E SOFT s t 1 0 1 3 6 1 0 ~1414~1
(69) 73 E SOFT s t 1 0 1 3 6 1 0 ~1420~1
- 90 F SOFT s t 1 0 1 3 6 1 0 ~1426~1
(27) 43 C SOFT s t 1 0 1 3 6 1 0 ~1432~1
- 2 A SOFT s t 1 0 1 3 6 1 0 ~1438~1
(33) 35 C SOFT s t 1 0 1 3 6 1 0 ~1444~1
(30) 38 C SOFT s t 0 0 0 0 2 1 0 ~1444~2
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\msmg\selects.rpt
selects
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+- LC2 ~1438~1
|
| Other LABs fed by signals
| that feed LAB 'A'
LC | | A B C D E F G H | Logic cells that feed LAB 'A':
Pin
139 -> - | - - - - - - - - | <-- clk
150 -> * | * - - - - - - * | <-- X11
160 -> * | * - - - - - - * | <-- X21
153 -> * | * - - - - - - * | <-- X31
LC113-> * | * - - - - - - * | <-- outp1
LC31 -> * | * * * * * * * * | <-- cont2
LC41 -> * | * * * * * * * * | <-- cont1
LC27 -> * | * * * * * * * * | <-- cont0
LC42 -> * | * * * * * * * * | <-- num1
LC26 -> * | * * * * * * * * | <-- num0
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\msmg\selects.rpt
selects
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+------------- LC20 data3
| +----------- LC24 data1
| | +--------- LC28 data0
| | | +------- LC31 cont2
| | | | +----- LC27 cont0
| | | | | +--- LC26 num0
| | | | | | +- LC18 ~1366~1
| | | | | | |
| | | | | | | Other LABs fed by signals
| | | | | | | that feed LAB 'B'
LC | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'B':
LC20 -> * * * - - - - | - * * * - - - * | <-- data3
LC24 -> * * - - - - - | - * * * - - - * | <-- data1
LC28 -> * * - - - - - | - * * * - - - * | <-- data0
LC31 -> - - - * - * * | * * * * * * * * | <-- cont2
LC27 -> - - - * * * * | * * * * * * * * | <-- cont0
LC26 -> - - - - - * * | * * * * * * * * | <-- num0
Pin
139 -> - - - - - - - | - - - - - - - - | <-- clk
30 -> - - - - - - * | - * - - - - - * | <-- X113
18 -> - - - - - - * | - * - - - - - * | <-- X213
15 -> - - - - - - * | - * - - - - - * | <-- X313
LC115-> - - - - - - * | - * - - - - - * | <-- outp13
LC34 -> * * - - - - - | - * * * - - - * | <-- data2
LC33 -> - - - - - * - | - * * * * * * * | <-- cont3
LC41 -> - - - * - * * | * * * * * * * * | <-- cont1
LC42 -> - - - - - - * | * * * * * * * * | <-- num1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\msmg\selects.rpt
selects
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'C':
Logic cells placed in LAB 'C'
+----------------- LC47 |LPM_ADD_SUB:1084|addcore:adder|addcore:adder0|result_node3
| +--------------- LC34 data2
| | +------------- LC33 cont3
| | | +----------- LC41 cont1
| | | | +--------- LC42 num1
| | | | | +------- LC46 ~1360~1
| | | | | | +----- LC43 ~1432~1
| | | | | | | +--- LC35 ~1444~1
| | | | | | | | +- LC38 ~1444~2
| | | | | | | | |
| | | | | | | | | Other LABs fed by signals
| | | | | | | | | that feed LAB 'C'
LC | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'C':
LC47 -> - - * - - - - - - | - - * - - - - - | <-- |LPM_ADD_SUB:1084|addcore:adder|addcore:adder0|result_node3
LC34 -> - * - - - - - - - | - * * * - - - * | <-- data2
LC33 -> * - * - * - - - * | - * * * * * * * | <-- cont3
LC41 -> * - * * * * * * - | * * * * * * * * | <-- cont1
LC42 -> - - - - * * * * - | * * * * * * * * | <-- num1
Pin
139 -> - - - - - - - - - | - - - - - - - - | <-- clk
151 -> - - - - - - - * - | - - * - - - - * | <-- X10
147 -> - - - - - - * - - | - - * - - - * - | <-- X12
149 -> - - - - - - - * - | - - * - - - - * | <-- X20
159 -> - - - - - - * - - | - - * - - - * - | <-- X22
158 -> - - - - - - - * - | - - * - - - - * | <-- X30
152 -> - - - - - - * - - | - - * - - - * - | <-- X32
33 -> - - - - - * - - - | - - * * - - - - | <-- X114
145 -> - - - - - * - - - | - - * * - - - - | <-- X214
14 -> - - - - - * - - - | - - * * - - - - | <-- X314
LC126-> - - - - - - - * * | - - * - - - - - | <-- outp0
LC99 -> - - - - - - * - - | - - * - - - * - | <-- outp2
LC49 -> - - - - - * - - - | - - * * - - - - | <-- outp14
LC20 -> - * - - - - - - - | - * * * - - - * | <-- data3
LC24 -> - * - - - - - - - | - * * * - - - * | <-- data1
LC28 -> - * - - - - - - - | - * * * - - - * | <-- data0
LC31 -> * - * - * * * * - | * * * * * * * * | <-- cont2
LC27 -> * - * * * * * * - | * * * * * * * * | <-- cont0
LC26 -> - - - - * * * * - | * * * * * * * * | <-- num0
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\msmg\selects.rpt
selects
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'D':
Logic cells placed in LAB 'D'
+------- LC49 outp14
| +----- LC51 sele1
| | +--- LC53 ~1354~1
| | | +- LC55 ~1372~1
| | | |
| | | | Other LABs fed by signals
| | | | that feed LAB 'D'
LC | | | | | A B C D E F G H | Logic cells that feed LAB 'D':
LC49 -> * - - - | - - * * - - - - | <-- outp14
LC51 -> - * - - | - - - * - - - - | <-- sele1
Pin
139 -> - - - - | - - - - - - - - | <-- clk
146 -> - - - * | - - - * - - * - | <-- X112
33 -> * - - - | - - * * - - - - | <-- X114
10 -> - - * - | - - - * - - * - | <-- X115
20 -> - - - * | - - - * - - * - | <-- X212
145 -> * - - - | - - * * - - - - | <-- X214
144 -> - - * - | - - - * - - * - | <-- X215
16 -> - - - * | - - - * - - * - | <-- X312
14 -> * - - - | - - * * - - - - | <-- X314
13 -> - - * - | - - - * - - * - | <-- X315
94 -> * - - - | - - - * - - - - | <-- X414
LC101-> - - - * | - - - * - - * - | <-- outp12
LC97 -> - - * - | - - - * - - * - | <-- outp15
LC20 -> - * - - | - * * * - - - * | <-- data3
LC34 -> - * - - | - * * * - - - * | <-- data2
LC24 -> - * - - | - * * * - - - * | <-- data1
LC28 -> - * - - | - * * * - - - * | <-- data0
LC33 -> * - - - | - * * * * * * * | <-- cont3
LC31 -> * - * * | * * * * * * * * | <-- cont2
LC41 -> * - * * | * * * * * * * * | <-- cont1
LC27 -> * - * * | * * * * * * * * | <-- cont0
LC42 -> * - * * | * * * * * * * * | <-- num1
LC26 -> * - * * | * * * * * * * * | <-- num0
LC46 -> * - - - | - - - * - - - - | <-- ~1360~1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\msmg\selects.rpt
selects
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'E':
Logic cells placed in LAB 'E'
+--------------- LC69 outp4
| +------------- LC68 outp5
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