📄 selects.rpt
字号:
Project Information e:\msmg\selects.rpt
MAX+plus II Compiler Report File
Version 10.0 9/14/2000
Compiled: 05/23/2008 14:08:37
Copyright (C) 1988-2000 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
SELECTS
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
selects EPM7128SQC160-6 65 20 0 48 15 37 %
User Pins: 65 20 0
Project Information e:\msmg\selects.rpt
** AUTO GLOBAL SIGNALS **
INFO: Signal 'clk' chosen for auto global Clock
Project Information e:\msmg\selects.rpt
** FILE HIERARCHY **
|lpm_add_sub:915|
|lpm_add_sub:915|addcore:adder|
|lpm_add_sub:915|addcore:adder|addcore:adder0|
|lpm_add_sub:915|altshift:result_ext_latency_ffs|
|lpm_add_sub:915|altshift:carry_ext_latency_ffs|
|lpm_add_sub:915|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:1084|
|lpm_add_sub:1084|addcore:adder|
|lpm_add_sub:1084|addcore:adder|addcore:adder0|
|lpm_add_sub:1084|altshift:result_ext_latency_ffs|
|lpm_add_sub:1084|altshift:carry_ext_latency_ffs|
|lpm_add_sub:1084|altshift:oflow_ext_latency_ffs|
Device-Specific Information: e:\msmg\selects.rpt
selects
***** Logic for device 'selects' compiled without errors.
Device: EPM7128SQC160-6
Device Options:
Turbo Bit = ON
Security Bit = OFF
Enable JTAG Support = ON
User Code = ffff
MultiVolt I/O = OFF
Device-Specific Information: e:\msmg\selects.rpt
selects
** ERROR SUMMARY **
Info: Chip 'selects' in device 'EPM7128SQC160-6' has less than 20% of pins available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
R R R R R R
E E E E E E
V S S S S S S o
C s o s s V E E E E E E u o
N N N N X X X C e u e e C R R R R R N N N N R t u
X X X . . . . X X X X X G X 1 2 2 I G G G c G l t l l C V V V V V . . . . V p t
2 2 3 C C C C 3 3 1 1 2 N 1 1 1 1 N N N N l N e p e e I E E E E E C C C C E 1 p
1 2 0 . . . . 1 2 0 1 0 D 2 2 4 5 T D D D k D 0 0 3 2 O D D D D D . . . . D 3 1
----------------------------------------------------------------------------------_
/ 160 158 156 154 152 150 148 146 144 142 140 138 136 134 132 130 128 126 124 122 |_
/ 159 157 155 153 151 149 147 145 143 141 139 137 135 133 131 129 127 125 123 121 |
N.C. | 1 120 | N.C.
N.C. | 2 119 | N.C.
N.C. | 3 118 | N.C.
N.C. | 4 117 | N.C.
N.C. | 5 116 | N.C.
N.C. | 6 115 | N.C.
N.C. | 7 114 | N.C.
VCCIO | 8 113 | GND
#TDI | 9 112 | #TDO
X115 | 10 111 | RESERVED
X211 | 11 110 | outp11
X110 | 12 109 | X415
X315 | 13 108 | X410
X314 | 14 107 | X36
X313 | 15 106 | X37
X312 | 16 105 | RESERVED
GND | 17 104 | VCCIO
X213 | 18 103 | outp12
X311 | 19 102 | X45
X212 | 20 101 | outp2
X111 | 21 EPM7128SQC160-6 100 | outp15
#TMS | 22 99 | #TCK
X34 | 23 98 | X26
X35 | 24 97 | outp9
X23 | 25 96 | X15
VCCIO | 26 95 | GND
X16 | 27 94 | X414
X13 | 28 93 | outp8
X19 | 29 92 | X413
X113 | 30 91 | outp10
X18 | 31 90 | X412
X17 | 32 89 | X411
X114 | 33 88 | X33
N.C. | 34 87 | N.C.
N.C. | 35 86 | N.C.
N.C. | 36 85 | N.C.
N.C. | 37 84 | N.C.
N.C. | 38 83 | N.C.
N.C. | 39 82 | N.C.
N.C. | 40 81 | N.C.
| 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 _|
\ 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 |
\-----------------------------------------------------------------------------------
X G X N N N N X X X X X X X V X X s o G V o o o o G X X X X X X X N N N N X V o
1 N 3 . . . . 2 2 2 4 4 2 4 C 2 2 e u N C u u u u N 4 3 4 4 4 3 4 . . . . 4 C u
4 D 1 C C C C 1 4 5 2 3 7 4 C 8 9 l t D C t t t t D 1 9 0 9 6 8 7 C C C C 8 C t
0 . . . . 0 I e p I p p p p . . . . I p
O 1 1 N 7 6 5 4 O 3
4 T
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: e:\msmg\selects.rpt
selects
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 1/16( 6%) 12/12(100%) 1/16( 6%) 9/36( 25%)
B: LC17 - LC32 7/16( 43%) 12/12(100%) 1/16( 6%) 14/36( 38%)
C: LC33 - LC48 9/16( 56%) 12/12(100%) 3/16( 18%) 23/36( 63%)
D: LC49 - LC64 4/16( 25%) 12/12(100%) 4/16( 25%) 25/36( 69%)
E: LC65 - LC80 8/16( 50%) 12/12(100%) 12/16( 75%) 30/36( 83%)
F: LC81 - LC96 9/16( 56%) 12/12(100%) 13/16( 81%) 34/36( 94%)
G: LC97 - LC112 4/16( 25%) 10/12( 83%) 8/16( 50%) 30/36( 83%)
H: LC113 - LC128 6/16( 37%) 6/12( 50%) 5/16( 31%) 31/36( 86%)
Total dedicated input pins used: 1/4 ( 25%)
Total I/O pins used: 88/96 ( 91%)
Total logic cells used: 48/128 ( 37%)
Total shareable expanders used: 15/128 ( 11%)
Total Turbo logic cells used: 48/128 ( 37%)
Total shareable expanders not available (n/a): 32/128 ( 25%)
Average fan-in: 8.89
Total fan-in: 427
Total input pins required: 65
Total fast input logic cells required: 0
Total output pins required: 20
Total bidirectional pins required: 0
Total reserved pins required 4
Total logic cells required: 48
Total flipflops required: 30
Total product terms required: 200
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 15
Synthesized logic cells: 17/ 128 ( 13%)
Device-Specific Information: e:\msmg\selects.rpt
selects
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
139 - - INPUT G 0 0 0 0 0 0 0 clk
151 (8) (A) INPUT 0 0 0 0 0 1 1 X10
150 (9) (A) INPUT 0 0 0 0 0 1 1 X11
147 (12) (A) INPUT 0 0 0 0 0 1 1 X12
28 (41) (C) INPUT 0 0 0 0 0 1 1 X13
41 (33) (C) INPUT 0 0 0 0 0 1 1 X14
96 (92) (F) INPUT 0 0 0 0 0 1 1 X15
27 (43) (C) INPUT 0 0 0 0 0 1 1 X16
32 (36) (C) INPUT 0 0 0 0 0 1 1 X17
31 (37) (C) INPUT 0 0 0 0 0 1 1 X18
29 (40) (C) INPUT 0 0 0 0 0 1 1 X19
149 (11) (A) INPUT 0 0 0 0 0 1 1 X20
160 (1) (A) INPUT 0 0 0 0 0 1 1 X21
159 (3) (A) INPUT 0 0 0 0 0 1 1 X22
25 (44) (C) INPUT 0 0 0 0 0 1 1 X23
49 (61) (D) INPUT 0 0 0 0 0 1 1 X24
50 (60) (D) INPUT 0 0 0 0 0 1 1 X25
98 (94) (F) INPUT 0 0 0 0 0 1 1 X26
53 (56) (D) INPUT 0 0 0 0 0 1 1 X27
56 (53) (D) INPUT 0 0 0 0 0 1 1 X28
57 (52) (D) INPUT 0 0 0 0 0 1 1 X29
158 (4) (A) INPUT 0 0 0 0 0 1 1 X30
153 (5) (A) INPUT 0 0 0 0 0 1 1 X31
152 (6) (A) INPUT 0 0 0 0 0 1 1 X32
88 (83) (F) INPUT 0 0 0 0 0 1 1 X33
23 (46) (C) INPUT 0 0 0 0 0 1 1 X34
24 (45) (C) INPUT 0 0 0 0 0 1 1 X35
107 (105) (G) INPUT 0 0 0 0 0 1 1 X36
106 (104) (G) INPUT 0 0 0 0 0 1 1 X37
72 (77) (E) INPUT 0 0 0 0 0 1 1 X38
68 (72) (E) INPUT 0 0 0 0 0 1 1 X39
69 (73) (E) INPUT 0 0 0 0 0 1 0 X40
67 (70) (E) INPUT 0 0 0 0 0 1 0 X41
51 (59) (D) INPUT 0 0 0 0 0 1 0 X42
52 (57) (D) INPUT 0 0 0 0 0 1 0 X43
54 (54) (D) INPUT 0 0 0 0 0 1 0 X44
102 (100) (G) INPUT 0 0 0 0 0 1 0 X45
71 (76) (E) INPUT 0 0 0 0 0 1 0 X46
73 (78) (E) INPUT 0 0 0 0 0 1 0 X47
78 (80) (E) INPUT 0 0 0 0 0 1 0 X48
70 (75) (E) INPUT 0 0 0 0 0 1 0 X49
12 (28) (B) INPUT 0 0 0 0 0 1 1 X110
21 (17) (B) INPUT 0 0 0 0 0 1 1 X111
146 (13) (A) INPUT 0 0 0 0 0 1 1 X112
30 (38) (C) INPUT 0 0 0 0 0 1 1 X113
33 (35) (C) INPUT 0 0 0 0 0 1 1 X114
10 (30) (B) INPUT 0 0 0 0 0 1 1 X115
48 (62) (D) INPUT 0 0 0 0 0 1 1 X210
11 (29) (B) INPUT 0 0 0 0 0 1 1 X211
20 (19) (B) INPUT 0 0 0 0 0 1 1 X212
18 (21) (B) INPUT 0 0 0 0 0 1 1 X213
145 (14) (A) INPUT 0 0 0 0 0 1 1 X214
144 (16) (A) INPUT 0 0 0 0 0 1 1 X215
43 (64) (D) INPUT 0 0 0 0 0 1 1 X310
19 (20) (B) INPUT 0 0 0 0 0 1 1 X311
16 (22) (B) INPUT 0 0 0 0 0 1 1 X312
15 (24) (B) INPUT 0 0 0 0 0 1 1 X313
14 (25) (B) INPUT 0 0 0 0 0 1 1 X314
13 (27) (B) INPUT 0 0 0 0 0 1 1 X315
108 (107) (G) INPUT 0 0 0 0 0 1 0 X410
89 (84) (F) INPUT 0 0 0 0 0 1 0 X411
90 (85) (F) INPUT 0 0 0 0 0 1 0 X412
92 (88) (F) INPUT 0 0 0 0 0 1 0 X413
94 (91) (F) INPUT 0 0 0 0 0 1 0 X414
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -