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📄 rz_msmg.rpt

📁 米字型数码管的编码方法。自动循环显示至少四个以上单词。
💻 RPT
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Device-Specific Information:                               e:\msmg\rz_msmg.rpt
rz_msmg

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'G':

                                         Logic cells placed in LAB 'G'
        +------------------------------- LC105 outp1
        | +----------------------------- LC99 outp2
        | | +--------------------------- LC97 outp14
        | | | +------------------------- LC100 |selects:U1|~1432~1
        | | | | +----------------------- LC101 |selects:U1|~1438~1
        | | | | | +--------------------- LC109 |select_word:U0|:28
        | | | | | | +------------------- LC98 |select_word:U0|:30
        | | | | | | | +----------------- LC104 |select_word:U0|:36
        | | | | | | | | +--------------- LC112 |select_word:U0|:60
        | | | | | | | | | +------------- LC111 |select_word:U0|:62
        | | | | | | | | | | +----------- LC106 |select_word:U0|:68
        | | | | | | | | | | | +--------- LC103 |select_word:U0|:92
        | | | | | | | | | | | | +------- LC102 |select_word:U0|:94
        | | | | | | | | | | | | | +----- LC107 |select_word:U0|:100
        | | | | | | | | | | | | | | +--- LC110 |select_word:U0|:124
        | | | | | | | | | | | | | | | +- LC108 |select_word:U0|:126
        | | | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | | | |   that feed LAB 'G'
LC      | | | | | | | | | | | | | | | | | A B C D E F G H |     Logic cells that feed LAB 'G':
LC105-> * - - - * - - - - - - - - - - - | - - - - - - * - | <-- outp1
LC99 -> - * - * - - - - - - - - - - - - | - - - - - - * - | <-- outp2
LC97 -> - - * - - - - - - - - - - - - - | - - - - - - * - | <-- outp14
LC100-> - * - - - - - - - - - - - - - - | - - - - - - * - | <-- |selects:U1|~1432~1
LC101-> * - - - - - - - - - - - - - - - | - - - - - - * - | <-- |selects:U1|~1438~1
LC109-> - * - * - * - - - - - - - - - - | - - - - - - * - | <-- |select_word:U0|:28
LC98 -> * - - - * - * - - - - - - - - - | - - - - - - * - | <-- |select_word:U0|:30
LC104-> - - * - - - - * - - - - - - - - | - - - - - - * - | <-- |select_word:U0|:36
LC112-> - * - * - - - - * - - - - - - - | - - - - - - * - | <-- |select_word:U0|:60
LC111-> * - - - * - - - - * - - - - - - | - - - - - - * - | <-- |select_word:U0|:62
LC106-> - - * - - - - - - - * - - - - - | - - - - - - * - | <-- |select_word:U0|:68
LC103-> - * - * - - - - - - - * - - - - | - - - - - - * - | <-- |select_word:U0|:92
LC102-> * - - - * - - - - - - - * - - - | - - - - - - * - | <-- |select_word:U0|:94
LC107-> - - * - - - - - - - - - - * - - | - - - - - - * - | <-- |select_word:U0|:100
LC110-> - * - - - - - - - - - - - - * - | - - - - - - * - | <-- |select_word:U0|:124
LC108-> * - - - - - - - - - - - - - - * | - - - - - - * - | <-- |select_word:U0|:126

Pin
83   -> - - - - - - - - - - - - - - - - | - - - - - - - - | <-- clk
LC27 -> * * * - - - - - - - - - - - - - | * * * * * * * * | <-- |selects:U1|cont3
LC10 -> * * * * * - - - - - - - - - - - | * * * * * * * * | <-- |selects:U1|cont2
LC9  -> * * * * * - - - - - - - - - - - | * * * * * * * * | <-- |selects:U1|cont1
LC26 -> * * * * * - - - - - - - - - - - | * * * * * * * * | <-- |selects:U1|cont0
LC116-> * * * * * - - - - - - - - - - - | * * * * * * * * | <-- |selects:U1|num1
LC113-> * * * * * - - - - - - - - - - - | * * * * * * * * | <-- |selects:U1|num0
LC49 -> - - * - - - - - - - - - - - - - | - - - * - - * - | <-- |select_word:U0|:4
LC77 -> - - - - - * * * * * * * * * * * | - - * * * * * * | <-- |select_word:U0|data2
LC122-> - - - - - * * * * * * * * * * * | - - * * * * * * | <-- |select_word:U0|data1
LC121-> - - - - - * * * * * * * * * * * | - - * * * * * * | <-- |select_word:U0|data0


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                               e:\msmg\rz_msmg.rpt
rz_msmg

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'H':

                                         Logic cells placed in LAB 'H'
        +------------------------------- LC123 outp0
        | +----------------------------- LC115 outp15
        | | +--------------------------- LC125 |selects:U1|LPM_ADD_SUB:1084|addcore:adder|addcore:adder0|result_node3
        | | | +------------------------- LC116 |selects:U1|num1
        | | | | +----------------------- LC113 |selects:U1|num0
        | | | | | +--------------------- LC114 |selects:U1|~1444~1
        | | | | | | +------------------- LC128 |select_word:U0|:2
        | | | | | | | +----------------- LC119 |select_word:U0|:32
        | | | | | | | | +--------------- LC120 |select_word:U0|:34
        | | | | | | | | | +------------- LC127 |select_word:U0|:64
        | | | | | | | | | | +----------- LC126 |select_word:U0|:66
        | | | | | | | | | | | +--------- LC117 |select_word:U0|:96
        | | | | | | | | | | | | +------- LC118 |select_word:U0|:98
        | | | | | | | | | | | | | +----- LC124 |select_word:U0|:128
        | | | | | | | | | | | | | | +--- LC122 |select_word:U0|data1
        | | | | | | | | | | | | | | | +- LC121 |select_word:U0|data0
        | | | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | | | |   that feed LAB 'H'
LC      | | | | | | | | | | | | | | | | | A B C D E F G H |     Logic cells that feed LAB 'H':
LC123-> * - - - - * - - - - - - - - - - | - - - - - - - * | <-- outp0
LC115-> - * - - - - - - - - - - - - - - | - - - - - - - * | <-- outp15
LC116-> * * - * - * - - - - - - - - - - | * * * * * * * * | <-- |selects:U1|num1
LC113-> * * - * * * - - - - - - - - - - | * * * * * * * * | <-- |selects:U1|num0
LC114-> * - - - - - - - - - - - - - - - | - - - - - - - * | <-- |selects:U1|~1444~1
LC128-> - * - - - - * - - - - - - - - - | - - - - - - - * | <-- |select_word:U0|:2
LC119-> * - - - - * - * - - - - - - - - | - - - - - - - * | <-- |select_word:U0|:32
LC120-> - * - - - - - - * - - - - - - - | - - - - - - - * | <-- |select_word:U0|:34
LC127-> * - - - - * - - - * - - - - - - | - - - - - - - * | <-- |select_word:U0|:64
LC126-> - * - - - - - - - - * - - - - - | - - - - - - - * | <-- |select_word:U0|:66
LC117-> * - - - - * - - - - - * - - - - | - - - - - - - * | <-- |select_word:U0|:96
LC118-> - * - - - - - - - - - - * - - - | - - - - - - - * | <-- |select_word:U0|:98
LC124-> * - - - - - - - - - - - - * - - | - - - - - - - * | <-- |select_word:U0|:128
LC122-> - - - - - - * * * * * * * * * * | - - * * * * * * | <-- |select_word:U0|data1
LC121-> - - - - - - * * * * * * * * * * | - - * * * * * * | <-- |select_word:U0|data0

Pin
83   -> - - - - - - - - - - - - - - - - | - - - - - - - - | <-- clk
LC27 -> * * * * * - - - - - - - - - - - | * * * * * * * * | <-- |selects:U1|cont3
LC10 -> * * * * * * - - - - - - - - - - | * * * * * * * * | <-- |selects:U1|cont2
LC9  -> * * * * * * - - - - - - - - - - | * * * * * * * * | <-- |selects:U1|cont1
LC26 -> * * * * * * - - - - - - - - - - | * * * * * * * * | <-- |selects:U1|cont0
LC77 -> - - - - - - * * * * * * * * - * | - - * * * * * * | <-- |select_word:U0|data2


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                               e:\msmg\rz_msmg.rpt
rz_msmg

** EQUATIONS **

clk      : INPUT;

-- Node name is 'outp0' = '|selects:U1|:104' 
-- Equation name is 'outp0', type is output 
 outp0   = DFFE( _EQ001 $  _EQ002, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ001 = !_LC009 & !_LC010 & !_LC026 & !_LC027 &  _LC113 & !_LC114 & 
              _LC116 & !_LC124 &  _X001
         # !_LC009 & !_LC010 & !_LC026 & !_LC027 & !_LC113 & !_LC114 & 
              _LC116 & !_LC117 &  _X001
         # !_LC009 & !_LC010 & !_LC026 & !_LC027 &  _LC113 & !_LC114 & 
             !_LC116 & !_LC127 &  _X001
         # !_LC009 & !_LC010 & !_LC026 & !_LC027 & !_LC113 & !_LC114 & 
             !_LC116 & !_LC119 &  _X001;
  _X001  = EXP( _LC027 & !outp0);
  _EQ002 = !_LC114 &  _X001;
  _X001  = EXP( _LC027 & !outp0);

-- Node name is 'outp1' = '|selects:U1|:102' 
-- Equation name is 'outp1', type is output 
 outp1   = DFFE( _EQ003 $  _EQ004, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ003 = !_LC009 & !_LC010 & !_LC026 & !_LC027 & !_LC101 & !_LC108 & 
              _LC113 &  _LC116 &  _X002
         # !_LC009 & !_LC010 & !_LC026 & !_LC027 & !_LC101 & !_LC102 & 
             !_LC113 &  _LC116 &  _X002
         # !_LC009 & !_LC010 & !_LC026 & !_LC027 & !_LC101 & !_LC111 & 
              _LC113 & !_LC116 &  _X002
         # !_LC009 & !_LC010 & !_LC026 & !_LC027 & !_LC098 & !_LC101 & 
             !_LC113 & !_LC116 &  _X002;
  _X002  = EXP( _LC027 & !outp1);
  _EQ004 = !_LC101 &  _X002;
  _X002  = EXP( _LC027 & !outp1);

-- Node name is 'outp2' = '|selects:U1|:100' 
-- Equation name is 'outp2', type is output 
 outp2   = DFFE( _EQ005 $  _EQ006, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ005 = !_LC009 & !_LC010 & !_LC026 & !_LC027 & !_LC100 & !_LC110 & 
              _LC113 &  _LC116 &  _X003
         # !_LC009 & !_LC010 & !_LC026 & !_LC027 & !_LC100 & !_LC103 & 
             !_LC113 &  _LC116 &  _X003
         # !_LC009 & !_LC010 & !_LC026 & !_LC027 & !_LC100 & !_LC112 & 
              _LC113 & !_LC116 &  _X003
         # !_LC009 & !_LC010 & !_LC026 & !_LC027 & !_LC100 & !_LC109 & 
             !_LC113 & !_LC116 &  _X003;
  _X003  = EXP( _LC027 & !outp2);
  _EQ006 = !_LC100 &  _X003;
  _X003  = EXP( _LC027 & !outp2);

-- Node name is 'outp3' = '|selects:U1|:98' 
-- Equation name is 'outp3', type is output 
 outp3   = DFFE( _EQ007 $  _EQ008, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ007 = !_LC009 & !_LC010 & !_LC026 & !_LC027 & !_LC096 &  _LC113 & 
              _LC116 &  _X004 &  _X005 &  _X006 &  _X007 &  _X008 &  _X009
         # !_LC009 & !_LC010 & !_LC026 & !_LC027 & !_LC085 & !_LC113 & 
              _LC116 &  _X004 &  _X005 &  _X006 &  _X007 &  _X008 &  _X009
         # !_LC009 & !_LC010 & !_LC026 & !_LC027 & !_LC087 &  _LC113 & 
             !_LC116 &  _X004 &  _X005 &  _X006 &  _X007 &  _X008 &  _X009
         # !_LC009 & !_LC010 & !_LC026 & !_LC027 & !_LC090 & !_LC113 & 
             !_LC116 &  _X004 &  _X005 &  _X006 &  _X007 &  _X008 &  _X009;
  _X004  = EXP(!_LC087 & !_LC090 & !_LC116 & !outp3);
  _X005  = EXP(!_LC085 & !_LC090 & !_LC113 & !outp3);
  _X006  = EXP( _LC026 & !outp3);
  _X007  = EXP( _LC009 & !outp3);
  _X008  = EXP( _LC010 & !outp3);
  _X009  = EXP( _LC027 & !outp3);
  _EQ008 =  _X004 &  _X005 &  _X006 &  _X007 &  _X008 &  _X009;
  _X004  = EXP(!_LC087 & !_LC090 & !_LC116 & !outp3);
  _X005  = EXP(!_LC085 & !_LC090 & !_LC113 & !outp3);
  _X006  = EXP( _LC026 & !outp3);
  _X007  = EXP( _LC009 & !outp3);
  _X008  = EXP( _LC010 & !outp3);
  _X009  = EXP( _LC027 & !outp3);

-- Node name is 'outp4' = '|selects:U1|:96' 
-- Equation name is 'outp4', type is output 
 outp4   = DFFE( _EQ009 $  _EQ010, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ009 = !_LC009 & !_LC010 & !_LC026 & !_LC027 & !_LC075 &  _LC113 & 
              _LC116 &  _X010 &  _X011 &  _X012 &  _X013 &  _X014 &  _X015
         # !_LC009 & !_LC010 & !_LC026 & !_LC027 & !_LC068 & !_LC113 & 
              _LC116 &  _X010 &  _X011 &  _X012 &  _X013 &  _X014 &  _X015
         # !_LC009 & !_LC010 & !_LC026 & !_LC027 & !_LC079 &  _LC113 & 
             !_LC116 &  _X010 &  _X011 &  _X012 &  _X013 &  _X014 &  _X015
         # !_LC009 & !_LC010 & !_LC026 & !_LC027 & !_LC067 & !_LC113 & 
             !_LC116 &  _X010 &  _X011 &  _X012 &  _X013 &  _X014 &  _X015;
  _X010  = EXP(!_LC067 & !_LC079 & !_LC116 & !outp4);
  _X011  = EXP(!_LC067 & !_LC068 & !_LC113 & !outp4);
  _X012  = EXP( _LC026 & !outp4);
  _X013  = EXP( _LC009 & !outp4);
  _X014  = EXP( _LC010 & !outp4);
  _X015  = EXP( _LC027 & !outp4);
  _EQ010 =  _X010 &  _X011 &  _X012 &  _X013 &  _X014 &  _X015;
  _X010  = EXP(!_LC067 & !_LC079 & !_LC116 & !outp4);
  _X011  = EXP(!_LC067 & !_LC068 & !_LC113 & !outp4);
  _X012  = EXP( _LC026 & !outp4);
  _X013  = EXP( _LC009 & !outp4);
  _X014  = EXP( _LC010 & !outp4);
  _X015  = EXP( _LC027 & !outp4);

-- Node name is 'outp5' = '|selects:U1|:94' 
-- Equation name is 'outp5', type is output 
 outp5   = DFFE( _EQ011 $  _EQ012, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ011 = !_LC009 & !_LC010 & !_LC026 & !_LC027 & !_LC061 &  _LC113 & 
              _LC116 &  _X016 &  _X017 &  _X018 &  _X019 &  _X020 &  _X021
         # !_LC009 & !_LC010 & !_LC026 & !_LC027 & !_LC058 & !_LC113 & 
              _LC116 &  _X016 &  _X017 &  _X018 &  _X019 &  _X020 &  _X021

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