📄 rz_msmg.rpt
字号:
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
77 123 H FF + t 2 0 1 0 12 1 1 outp0
68 105 G FF + t 2 0 1 0 12 1 1 outp1
64 99 G FF + t 2 0 1 0 12 1 1 outp2
58 91 F FF + t 7 0 1 0 11 1 0 outp3
49 73 E FF + t 7 0 1 0 11 1 0 outp4
36 57 D FF + t 7 0 1 0 11 1 0 outp5
12 3 A FF + t 7 0 1 0 11 1 0 outp6
22 17 B FF + t 7 0 1 0 11 1 0 outp7
31 35 C FF + t 7 0 1 0 11 1 0 outp8
30 37 C FF + t 7 0 1 0 11 1 0 outp9
21 19 B FF + t 7 0 1 0 11 1 0 outp10
40 51 D FF + t 7 0 1 0 11 1 0 outp11
60 93 F FF + t 7 0 1 0 11 1 0 outp12
48 72 E FF + t 7 0 1 0 11 1 0 outp13
63 97 G FF + t 7 0 1 0 11 1 0 outp14
73 115 H FF + t 7 0 1 0 11 1 0 outp15
24 46 C FF + t 0 0 0 0 5 1 0 sele0
29 38 C FF + t 0 0 0 0 5 1 0 sele1
25 45 C FF + t 0 0 0 0 5 1 0 sele2
27 43 C FF + t 0 0 0 0 5 1 0 sele3
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\msmg\rz_msmg.rpt
rz_msmg
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
(79) 125 H SOFT t 0 0 0 0 4 0 1 |selects:U1|LPM_ADD_SUB:1084|addcore:adder|addcore:adder0|result_node3
- 47 C DFFE + t 0 0 0 0 4 4 4 |selects:U1|data3 (|selects:U1|:106)
- 44 C DFFE + t 0 0 0 0 4 4 3 |selects:U1|data2 (|selects:U1|:107)
- 42 C DFFE + t 0 0 0 0 4 4 3 |selects:U1|data1 (|selects:U1|:108)
(28) 40 C DFFE + t 0 0 0 0 1 4 3 |selects:U1|data0 (|selects:U1|:109)
(16) 27 B DFFE + t 0 0 0 0 5 16 4 |selects:U1|cont3 (|selects:U1|:110)
- 10 A TFFE + t 0 0 0 0 2 16 7 |selects:U1|cont2 (|selects:U1|:111)
- 9 A TFFE + t 0 0 0 0 1 16 8 |selects:U1|cont1 (|selects:U1|:112)
- 26 B TFFE + t 0 0 0 0 0 16 9 |selects:U1|cont0 (|selects:U1|:113)
- 116 H TFFE + t 0 0 0 0 5 16 3 |selects:U1|num1 (|selects:U1|:114)
- 113 H TFFE + t 0 0 0 0 4 16 4 |selects:U1|num0 (|selects:U1|:115)
- 100 G SOFT s t 1 0 1 0 9 1 0 |selects:U1|~1432~1
(65) 101 G SOFT s t 1 0 1 0 9 1 0 |selects:U1|~1438~1
- 114 H SOFT s t 1 0 1 0 9 1 0 |selects:U1|~1444~1
- 84 F SOFT t 0 0 0 0 3 0 1 |select_word:U0|LPM_ADD_SUB:488|addcore:adder|addcore:adder0|result_node2
(81) 128 H DFFE + t 0 0 0 0 4 1 1 |select_word:U0|:2
(41) 49 D DFFE + t 0 0 0 0 4 1 1 |select_word:U0|:4
- 70 E DFFE + t 0 0 0 0 4 1 1 |select_word:U0|:6
(61) 94 F DFFE + t 0 0 0 0 4 1 1 |select_word:U0|:8
(33) 64 D DFFE + t 0 0 0 0 4 1 1 |select_word:U0|:10
- 82 F DFFE + t 0 0 0 0 4 1 1 |select_word:U0|:12
- 50 D DFFE + t 0 0 0 0 4 1 1 |select_word:U0|:14
- 52 D DFFE + t 0 0 0 0 4 1 1 |select_word:U0|:16
- 81 F DFFE + t 0 0 0 0 4 1 1 |select_word:U0|:18
(54) 83 F DFFE + t 0 0 0 0 4 1 1 |select_word:U0|:20
(39) 53 D DFFE + t 0 0 0 0 4 1 1 |select_word:U0|:22
(45) 67 E DFFE + t 0 0 0 0 4 1 1 |select_word:U0|:24
- 90 F DFFE + t 0 0 0 0 4 1 1 |select_word:U0|:26
(70) 109 G DFFE + t 0 0 0 0 4 1 2 |select_word:U0|:28
- 98 G DFFE + t 0 0 0 0 4 1 2 |select_word:U0|:30
- 119 H DFFE + t 0 0 0 0 4 1 2 |select_word:U0|:32
(76) 120 H DFFE + t 0 0 0 0 4 1 1 |select_word:U0|:34
(67) 104 G DFFE + t 0 0 0 0 4 1 1 |select_word:U0|:36
(52) 80 E DFFE + t 0 0 0 0 4 1 1 |select_word:U0|:38
(56) 86 F DFFE + t 0 0 0 0 4 1 1 |select_word:U0|:40
- 54 D DFFE + t 0 0 0 0 4 1 1 |select_word:U0|:42
(44) 65 E DFFE + t 0 0 0 0 4 1 1 |select_word:U0|:44
- 39 C DFFE + t 0 0 0 0 4 1 1 |select_word:U0|:46
(23) 48 C DFFE + t 0 0 0 0 4 1 1 |select_word:U0|:48
- 66 E DFFE + t 0 0 0 0 4 1 1 |select_word:U0|:50
- 74 E DFFE + t 0 0 0 0 4 1 1 |select_word:U0|:52
(35) 59 D DFFE + t 0 0 0 0 4 1 1 |select_word:U0|:54
- 79 E DFFE + t 0 0 0 0 4 1 1 |select_word:U0|:56
- 87 F DFFE + t 0 0 0 0 4 1 1 |select_word:U0|:58
(71) 112 G DFFE + t 0 0 0 0 4 1 2 |select_word:U0|:60
- 111 G DFFE + t 0 0 0 0 4 1 2 |select_word:U0|:62
- 127 H DFFE + t 0 0 0 0 4 1 2 |select_word:U0|:64
(80) 126 H DFFE + t 0 0 0 0 4 1 1 |select_word:U0|:66
- 106 G DFFE + t 0 0 0 0 4 1 1 |select_word:U0|:68
- 71 E DFFE + t 0 0 0 0 4 1 1 |select_word:U0|:70
- 92 F DFFE + t 0 0 0 0 4 1 1 |select_word:U0|:72
- 62 D DFFE + t 0 0 0 0 4 1 1 |select_word:U0|:74
- 76 E DFFE + t 0 0 0 0 4 1 1 |select_word:U0|:76
- 36 C DFFE + t 0 0 0 0 4 1 1 |select_word:U0|:78
- 34 C DFFE + t 0 0 0 0 4 1 1 |select_word:U0|:80
- 60 D DFFE + t 0 0 0 0 4 1 1 |select_word:U0|:82
(37) 56 D DFFE + t 0 0 0 0 4 1 1 |select_word:U0|:84
- 58 D DFFE + t 0 0 0 0 4 1 1 |select_word:U0|:86
- 68 E DFFE + t 0 0 0 0 4 1 1 |select_word:U0|:88
(55) 85 F DFFE + t 0 0 0 0 4 1 1 |select_word:U0|:90
- 103 G DFFE + t 0 0 0 0 4 1 2 |select_word:U0|:92
- 102 G DFFE + t 0 0 0 0 4 1 2 |select_word:U0|:94
(74) 117 H DFFE + t 0 0 0 0 4 1 2 |select_word:U0|:96
(75) 118 H DFFE + t 0 0 0 0 4 1 1 |select_word:U0|:98
(69) 107 G DFFE + t 0 0 0 0 4 1 1 |select_word:U0|:100
(46) 69 E DFFE + t 0 0 0 0 4 1 1 |select_word:U0|:102
(57) 88 F DFFE + t 0 0 0 0 4 1 1 |select_word:U0|:104
- 63 D DFFE + t 0 0 0 0 4 1 1 |select_word:U0|:106
- 55 D DFFE + t 0 0 0 0 4 1 1 |select_word:U0|:108
- 33 C DFFE + t 0 0 0 0 4 1 1 |select_word:U0|:110
- 41 C DFFE + t 0 0 0 0 4 1 1 |select_word:U0|:112
- 89 F DFFE + t 0 0 0 0 4 1 1 |select_word:U0|:114
- 78 E DFFE + t 0 0 0 0 4 1 1 |select_word:U0|:116
(34) 61 D DFFE + t 0 0 0 0 4 1 1 |select_word:U0|:118
(50) 75 E DFFE + t 0 0 0 0 4 1 1 |select_word:U0|:120
(62) 96 F DFFE + t 0 0 0 0 4 1 1 |select_word:U0|:122
- 110 G DFFE + t 0 0 0 0 4 1 1 |select_word:U0|:124
- 108 G DFFE + t 0 0 0 0 4 1 1 |select_word:U0|:126
- 124 H DFFE + t 0 0 0 0 4 1 1 |select_word:U0|:128
(51) 77 E DFFE + t 0 0 0 0 4 0 67 |select_word:U0|data2 (|select_word:U0|:130)
- 122 H TFFE + t 0 0 0 0 1 0 67 |select_word:U0|data1 (|select_word:U0|:131)
- 121 H TFFE + t 0 0 0 0 3 0 68 |select_word:U0|data0 (|select_word:U0|:132)
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\msmg\rz_msmg.rpt
rz_msmg
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+----- LC3 outp6
| +--- LC10 |selects:U1|cont2
| | +- LC9 |selects:U1|cont1
| | |
| | | Other LABs fed by signals
| | | that feed LAB 'A'
LC | | | | A B C D E F G H | Logic cells that feed LAB 'A':
LC3 -> * - - | * - - - - - - - | <-- outp6
LC10 -> * * - | * * * * * * * * | <-- |selects:U1|cont2
LC9 -> * * * | * * * * * * * * | <-- |selects:U1|cont1
Pin
83 -> - - - | - - - - - - - - | <-- clk
LC27 -> * - - | * * * * * * * * | <-- |selects:U1|cont3
LC26 -> * * * | * * * * * * * * | <-- |selects:U1|cont0
LC116-> * - - | * * * * * * * * | <-- |selects:U1|num1
LC113-> * - - | * * * * * * * * | <-- |selects:U1|num0
LC83 -> * - - | * - - - - * - - | <-- |select_word:U0|:20
LC74 -> * - - | * - - - * - - - | <-- |select_word:U0|:52
LC56 -> * - - | * - - * - - - - | <-- |select_word:U0|:84
LC78 -> * - - | * - - - * - - - | <-- |select_word:U0|:116
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\msmg\rz_msmg.rpt
rz_msmg
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+------- LC17 outp7
| +----- LC19 outp10
| | +--- LC27 |selects:U1|cont3
| | | +- LC26 |selects:U1|cont0
| | | |
| | | | Other LABs fed by signals
| | | | that feed LAB 'B'
LC | | | | | A B C D E F G H | Logic cells that feed LAB 'B':
LC17 -> * - - - | - * - - - - - - | <-- outp7
LC19 -> - * - - | - * - - - - - - | <-- outp10
LC27 -> * * * - | * * * * * * * * | <-- |selects:U1|cont3
LC26 -> * * * * | * * * * * * * * | <-- |selects:U1|cont0
Pin
83 -> - - - - | - - - - - - - - | <-- clk
LC125-> - - * - | - * - - - - - - | <-- |selects:U1|LPM_ADD_SUB:1084|addcore:adder|addcore:adder0|result_node3
LC10 -> * * * - | * * * * * * * * | <-- |selects:U1|cont2
LC9 -> * * * - | * * * * * * * * | <-- |selects:U1|cont1
LC116-> * * - - | * * * * * * * * | <-- |selects:U1|num1
LC113-> * * - - | * * * * * * * * | <-- |selects:U1|num0
LC82 -> - * - - | - * - - - * - - | <-- |select_word:U0|:12
LC81 -> * - - - | - * - - - * - - | <-- |select_word:U0|:18
LC65 -> - * - - | - * - - * - - - | <-- |select_word:U0|:44
LC66 -> * - - - | - * - - * - - - | <-- |select_word:U0|:50
LC76 -> - * - - | - * - - * - - - | <-- |select_word:U0|:76
LC60 -> * - - - | - * - * - - - - | <-- |select_word:U0|:82
LC55 -> - * - - | - * - * - - - - | <-- |select_word:U0|:108
LC89 -> * - - - | - * - - - * - - | <-- |select_word:U0|:114
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\msmg\rz_msmg.rpt
rz_msmg
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'C':
Logic cells placed in LAB 'C'
+------------------------------- LC35 outp8
| +----------------------------- LC37 outp9
| | +--------------------------- LC47 |selects:U1|data3
| | | +------------------------- LC44 |selects:U1|data2
| | | | +----------------------- LC42 |selects:U1|data1
| | | | | +--------------------- LC40 |selects:U1|data0
| | | | | | +------------------- LC39 |select_word:U0|:46
| | | | | | | +----------------- LC48 |select_word:U0|:48
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -