📄 rz_msmg.rpt
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Project Information e:\msmg\rz_msmg.rpt
MAX+plus II Compiler Report File
Version 10.0 9/14/2000
Compiled: 05/23/2008 14:14:09
Copyright (C) 1988-2000 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
RZ_MSMG
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
rz_msmg EPM7128SLC84-6 1 20 0 102 81 79 %
User Pins: 1 20 0
Project Information e:\msmg\rz_msmg.rpt
** AUTO GLOBAL SIGNALS **
INFO: Signal 'clk' chosen for auto global Clock
Project Information e:\msmg\rz_msmg.rpt
** FILE HIERARCHY **
|select_word:U0|
|select_word:U0|lpm_add_sub:488|
|select_word:U0|lpm_add_sub:488|addcore:adder|
|select_word:U0|lpm_add_sub:488|addcore:adder|addcore:adder0|
|select_word:U0|lpm_add_sub:488|altshift:result_ext_latency_ffs|
|select_word:U0|lpm_add_sub:488|altshift:carry_ext_latency_ffs|
|select_word:U0|lpm_add_sub:488|altshift:oflow_ext_latency_ffs|
|selects:U1|
|selects:U1|lpm_add_sub:915|
|selects:U1|lpm_add_sub:915|addcore:adder|
|selects:U1|lpm_add_sub:915|addcore:adder|addcore:adder0|
|selects:U1|lpm_add_sub:915|altshift:result_ext_latency_ffs|
|selects:U1|lpm_add_sub:915|altshift:carry_ext_latency_ffs|
|selects:U1|lpm_add_sub:915|altshift:oflow_ext_latency_ffs|
|selects:U1|lpm_add_sub:1084|
|selects:U1|lpm_add_sub:1084|addcore:adder|
|selects:U1|lpm_add_sub:1084|addcore:adder|addcore:adder0|
|selects:U1|lpm_add_sub:1084|altshift:result_ext_latency_ffs|
|selects:U1|lpm_add_sub:1084|altshift:carry_ext_latency_ffs|
|selects:U1|lpm_add_sub:1084|altshift:oflow_ext_latency_ffs|
Device-Specific Information: e:\msmg\rz_msmg.rpt
rz_msmg
***** Logic for device 'rz_msmg' compiled without errors.
Device: EPM7128SLC84-6
Device Options:
Turbo Bit = ON
Security Bit = OFF
Enable JTAG Support = ON
User Code = ffff
MultiVolt I/O = OFF
R R R R R R R R R R R R
E E E E E E E E E E E E
S S S S S S S V S S S S S
E E E E E E E C E E E V o E E
R R R R R R R C R R R C u R R
V V V V G V V V I G G G c G V V V C t V V
E E E E N E E E N N N N l N E E E I p E E
D D D D D D D D T D D D k D D D D O 0 D D
-----------------------------------------------------------------_
/ 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 |
outp6 | 12 74 | RESERVED
VCCIO | 13 73 | outp15
#TDI | 14 72 | GND
RESERVED | 15 71 | #TDO
RESERVED | 16 70 | RESERVED
RESERVED | 17 69 | RESERVED
RESERVED | 18 68 | outp1
GND | 19 67 | RESERVED
RESERVED | 20 66 | VCCIO
outp10 | 21 65 | RESERVED
outp7 | 22 EPM7128SLC84-6 64 | outp2
#TMS | 23 63 | outp14
sele0 | 24 62 | #TCK
sele2 | 25 61 | RESERVED
VCCIO | 26 60 | outp12
sele3 | 27 59 | GND
RESERVED | 28 58 | outp3
sele1 | 29 57 | RESERVED
outp9 | 30 56 | RESERVED
outp8 | 31 55 | RESERVED
GND | 32 54 | RESERVED
|_ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 _|
------------------------------------------------------------------
R R R o R V R o R G V R R R G o o R R R V
E E E u E C E u E N C E E E N u u E E E C
S S S t S C S t S D C S S S D t t S S S C
E E E p E I E p E I E E E p p E E E I
R R R 5 R O R 1 R N R R R 1 4 R R R O
V V V V V 1 V T V V V 3 V V V
E E E E E E E E E E E E
D D D D D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: e:\msmg\rz_msmg.rpt
rz_msmg
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 3/16( 18%) 1/ 8( 12%) 7/16( 43%) 11/36( 30%)
B: LC17 - LC32 4/16( 25%) 3/ 8( 37%) 14/16( 87%) 17/36( 47%)
C: LC33 - LC48 16/16(100%) 7/ 8( 87%) 14/16( 87%) 27/36( 75%)
D: LC49 - LC64 16/16(100%) 2/ 8( 25%) 14/16( 87%) 25/36( 69%)
E: LC65 - LC80 16/16(100%) 2/ 8( 25%) 14/16( 87%) 25/36( 69%)
F: LC81 - LC96 15/16( 93%) 3/ 8( 37%) 14/16( 87%) 23/36( 63%)
G: LC97 - LC112 16/16(100%) 4/ 8( 50%) 13/16( 81%) 26/36( 72%)
H: LC113 - LC128 16/16(100%) 2/ 8( 25%) 10/16( 62%) 20/36( 55%)
Total dedicated input pins used: 1/4 ( 25%)
Total I/O pins used: 24/64 ( 37%)
Total logic cells used: 102/128 ( 79%)
Total shareable expanders used: 81/128 ( 63%)
Total Turbo logic cells used: 102/128 ( 79%)
Total shareable expanders not available (n/a): 19/128 ( 14%)
Average fan-in: 6.17
Total fan-in: 630
Total input pins required: 1
Total fast input logic cells required: 0
Total output pins required: 20
Total bidirectional pins required: 0
Total reserved pins required 4
Total logic cells required: 102
Total flipflops required: 97
Total product terms required: 405
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 81
Synthesized logic cells: 3/ 128 ( 2%)
Device-Specific Information: e:\msmg\rz_msmg.rpt
rz_msmg
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
83 - - INPUT G 0 0 0 0 0 0 0 clk
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: e:\msmg\rz_msmg.rpt
rz_msmg
** OUTPUTS **
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