📄 selects.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity selects is
port(clk : in std_logic;
X1,X2,X3,X4 : in std_logic_vector(15 downto 0);
sele : out std_logic_vector(3 downto 0);
outp : out std_logic_vector(15 downto 0));
end entity selects;
architecture art of selects is
signal data : std_logic_vector(3 downto 0);
signal cont : std_logic_vector(3 downto 0);
signal num : std_logic_vector(1 downto 0);
begin
process (clk) is
begin
if (clk'event and clk = '1') then
if data = "0000" then
data <= "1110";
else
data <= data(2 downto 0) & data(3);
sele <= data;
end if;
if cont = "0000" then
cont <= "1111";
if num = "11" then
num <= "00";
outp <= X4;
else
case num is
when "00" => outp <= X1;
when "01" => outp <= X2;
when "10" => outp <= X3;
when "11" => outp <= X4;
when others => null;
end case;
num <= num + 1;
end if;
else
cont <= cont - 1;
end if;
end if;
end process;
end architecture art;
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