📄 select_word.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity select_word is
port( clk : in std_logic;
X1,X2,X3,X4 : out std_logic_vector(15 downto 0));
end entity select_word;
architecture art of select_word is
signal data : std_logic_vector(2 downto 0);
signal cont : std_logic_vector(3 downto 0);
begin
process (clk) is
begin
if clk'event and clk='1' then
if cont = "0000" then
cont <= "1111";
if data = "100" then
data <= "000";
else
data <= data + 1;
end if;
case data is
when "000" => x1<=X"0000"; x2<=X"4a00"; x3<=X"0acc"; x4<=X"0000"; --" MY "
when "001" => x1<=X"11f3"; x2<=X"0acc"; x3<=X"11cf"; x4<=X"22cc"; --"NAME"
when "010" => x1<=X"0000"; x2<=X"11bb"; x3<=X"4433"; x4<=X"0000"; --" IS "
when "011" => x1<=X"22cc"; x2<=X"11cf"; x3<=X"31c7"; x4<=X"0000"; --" RAN"
when "100" => x1<=X"22cc"; x2<=X"11f3"; x3<=X"11cc"; x4<=X"8833"; --"ZHEN"
when others => null;
end case;
else
cont <= cont - 1;
end if;
end if;
end process;
end architecture art;
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