📄 select_word.rpt
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Project Information e:\msmg\select_word.rpt
MAX+plus II Compiler Report File
Version 10.0 9/14/2000
Compiled: 05/23/2008 14:21:06
Copyright (C) 1988-2000 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
SELECT_WORD
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
select_word
EPM7128SQC100-6 1 64 0 72 0 56 %
User Pins: 1 64 0
Project Information e:\msmg\select_word.rpt
** AUTO GLOBAL SIGNALS **
INFO: Signal 'clk' chosen for auto global Clock
Project Information e:\msmg\select_word.rpt
** FILE HIERARCHY **
|lpm_add_sub:518|
|lpm_add_sub:518|addcore:adder|
|lpm_add_sub:518|addcore:adder|addcore:adder0|
|lpm_add_sub:518|altshift:result_ext_latency_ffs|
|lpm_add_sub:518|altshift:carry_ext_latency_ffs|
|lpm_add_sub:518|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:2462|
|lpm_add_sub:2462|addcore:adder|
|lpm_add_sub:2462|addcore:adder|addcore:adder0|
|lpm_add_sub:2462|altshift:result_ext_latency_ffs|
|lpm_add_sub:2462|altshift:carry_ext_latency_ffs|
|lpm_add_sub:2462|altshift:oflow_ext_latency_ffs|
Device-Specific Information: e:\msmg\select_word.rpt
select_word
***** Logic for device 'select_word' compiled without errors.
Device: EPM7128SQC100-6
Device Options:
Turbo Bit = ON
Security Bit = OFF
Enable JTAG Support = ON
User Code = ffff
MultiVolt I/O = OFF
R R R R R R R
E E E E E E E
S S S S S S V S
E E E E E E C V E
R R R R R R C C R
V V V G V V V I G G G c G X X X C V X X
E E E N E E E N N N N l N 1 1 1 I E 1 1
D D D D D D D T D D D k D 7 0 3 O D 4 6
------------------------------------------_
/ 100 98 96 94 92 90 88 86 84 82 |_
/ 99 97 95 93 91 89 87 85 83 81 |
RESERVED | 1 80 | X15
RESERVED | 2 79 | X18
RESERVED | 3 78 | X12
RESERVED | 4 77 | X11
VCCIO | 5 76 | GND
#TDI | 6 75 | #TDO
X412 | 7 74 | X20
X413 | 8 73 | X23
X415 | 9 72 | X21
X410 | 10 71 | X24
RESERVED | 11 70 | X25
X414 | 12 69 | X26
GND | 13 68 | VCCIO
X315 | 14 67 | X19
X411 | 15 66 | X22
X314 | 16 EPM7128SQC100-6 65 | X27
#TMS | 17 64 | #TCK
X312 | 18 63 | X35
X213 | 19 62 | X36
VCCIO | 20 61 | GND
X211 | 21 60 | X34
X310 | 22 59 | X33
X215 | 23 58 | X28
X311 | 24 57 | X29
X214 | 25 56 | X30
X212 | 26 55 | X31
X313 | 27 54 | X32
GND | 28 53 | VCCIO
X114 | 29 52 | X39
X48 | 30 51 | X40
| 32 34 36 38 40 42 44 46 48 50 _|
\ 31 33 35 37 39 41 43 45 47 49 |
\-------------------------------------------
X X X X X V X X X G V X X X G X X X X X
2 4 1 1 1 C 1 4 1 N C 4 3 3 N 4 4 4 4 4
1 9 1 1 1 C 1 7 1 D C 3 8 7 D 4 5 2 1 6
0 1 5 0 I 2 3 I
O N
T
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: e:\msmg\select_word.rpt
select_word
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 0/16( 0%) 0/10( 0%) 0/16( 0%) 0/36( 0%)
B: LC17 - LC32 8/16( 50%) 9/10( 90%) 0/16( 0%) 15/36( 41%)
C: LC33 - LC48 9/16( 56%) 10/10(100%) 0/16( 0%) 16/36( 44%)
D: LC49 - LC64 10/16( 62%) 10/10(100%) 0/16( 0%) 17/36( 47%)
E: LC65 - LC80 10/16( 62%) 10/10(100%) 0/16( 0%) 17/36( 47%)
F: LC81 - LC96 9/16( 56%) 10/10(100%) 0/16( 0%) 16/36( 44%)
G: LC97 - LC112 10/16( 62%) 10/10(100%) 0/16( 0%) 17/36( 47%)
H: LC113 - LC128 16/16(100%) 9/10( 90%) 0/16( 0%) 16/36( 44%)
Total dedicated input pins used: 1/4 ( 25%)
Total I/O pins used: 68/80 ( 85%)
Total logic cells used: 72/128 ( 56%)
Total shareable expanders used: 0/128 ( 0%)
Total Turbo logic cells used: 72/128 ( 56%)
Total shareable expanders not available (n/a): 0/128 ( 0%)
Average fan-in: 8.58
Total fan-in: 618
Total input pins required: 1
Total fast input logic cells required: 0
Total output pins required: 64
Total bidirectional pins required: 0
Total reserved pins required 4
Total logic cells required: 72
Total flipflops required: 71
Total product terms required: 198
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 0
Synthesized logic cells: 0/ 128 ( 0%)
Device-Specific Information: e:\msmg\select_word.rpt
select_word
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
89 - - INPUT G 0 0 0 0 0 0 0 clk
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: e:\msmg\select_word.rpt
select_word
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
86 126 H FF + t 0 0 0 0 8 1 0 X10
77 113 H FF + t 0 0 0 0 8 1 0 X11
78 115 H FF + t 0 0 0 0 8 1 0 X12
85 125 H FF + t 0 0 0 0 8 1 0 X13
82 121 H FF + t 0 0 0 0 8 1 0 X14
80 118 H FF + t 0 0 0 0 8 1 0 X15
81 120 H FF + t 0 0 0 0 8 1 0 X16
87 128 H FF + t 0 0 0 0 8 1 0 X17
79 117 H FF + t 0 0 0 0 8 1 0 X18
67 101 G FF + t 0 0 0 0 8 1 0 X19
74 110 G FF + t 0 0 0 0 8 1 0 X20
72 107 G FF + t 0 0 0 0 8 1 0 X21
66 99 G FF + t 0 0 0 0 8 1 0 X22
73 109 G FF + t 0 0 0 0 8 1 0 X23
71 105 G FF + t 0 0 0 0 8 1 0 X24
70 104 G FF + t 0 0 0 0 8 1 0 X25
69 102 G FF + t 0 0 0 0 8 1 0 X26
65 97 G FF + t 0 0 0 0 8 1 0 X27
58 88 F FF + t 0 0 0 0 8 1 0 X28
57 86 F FF + t 0 0 0 0 8 1 0 X29
56 85 F FF + t 0 0 0 0 8 1 0 X30
55 83 F FF + t 0 0 0 0 8 1 0 X31
54 81 F FF + t 0 0 0 0 8 1 0 X32
59 89 F FF + t 0 0 0 0 8 1 0 X33
60 91 F FF + t 0 0 0 0 8 1 0 X34
63 94 F FF + t 0 0 0 0 8 1 0 X35
62 93 F FF + t 0 0 0 0 8 1 0 X36
44 69 E FF + t 0 0 0 0 8 1 0 X37
43 67 E FF + t 0 0 0 0 8 1 0 X38
52 80 E FF + t 0 0 0 0 8 1 0 X39
51 78 E FF + t 0 0 0 0 8 1 0 X40
49 75 E FF + t 0 0 0 0 8 1 0 X41
48 73 E FF + t 0 0 0 0 8 1 0 X42
42 65 E FF + t 0 0 0 0 8 1 0 X43
46 70 E FF + t 0 0 0 0 8 1 0 X44
47 72 E FF + t 0 0 0 0 8 1 0 X45
50 77 E FF + t 0 0 0 0 8 1 0 X46
38 51 D FF + t 0 0 0 0 8 1 0 X47
30 62 D FF + t 0 0 0 0 8 1 0 X48
32 59 D FF + t 0 0 0 0 8 1 0 X49
35 54 D FF + t 0 0 0 0 8 1 0 X110
33 57 D FF + t 0 0 0 0 8 1 0 X111
37 53 D FF + t 0 0 0 0 8 1 0 X112
39 49 D FF + t 0 0 0 0 8 1 0 X113
29 64 D FF + t 0 0 0 0 8 1 0 X114
34 56 D FF + t 0 0 0 0 8 1 0 X115
31 61 D FF + t 0 0 0 0 8 1 0 X210
21 43 C FF + t 0 0 0 0 8 1 0 X211
26 35 C FF + t 0 0 0 0 8 1 0 X212
19 45 C FF + t 0 0 0 0 8 1 0 X213
25 37 C FF + t 0 0 0 0 8 1 0 X214
23 40 C FF + t 0 0 0 0 8 1 0 X215
22 41 C FF + t 0 0 0 0 8 1 0 X310
24 38 C FF + t 0 0 0 0 8 1 0 X311
18 46 C FF + t 0 0 0 0 8 1 0 X312
27 33 C FF + t 0 0 0 0 8 1 0 X313
16 17 B FF + t 0 0 0 0 8 1 0 X314
14 21 B FF + t 0 0 0 0 8 1 0 X315
10 25 B FF + t 0 0 0 0 8 1 0 X410
15 19 B FF + t 0 0 0 0 8 1 0 X411
7 30 B FF + t 0 0 0 0 8 1 0 X412
8 29 B FF + t 0 0 0 0 8 1 0 X413
12 22 B FF + t 0 0 0 0 8 1 0 X414
9 27 B FF + t 0 0 0 0 8 1 0 X415
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\msmg\select_word.rpt
select_word
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
- 119 H SOFT t 0 0 0 0 4 0 1 |LPM_ADD_SUB:2462|addcore:adder|addcore:adder0|result_node3
- 108 G DFFE + t 0 0 0 0 5 64 5 cont3 (:130)
- 116 H TFFE + t 0 0 0 0 2 64 5 cont2 (:131)
- 122 H TFFE + t 0 0 0 0 1 64 6 cont1 (:132)
- 127 H TFFE + t 0 0 0 0 0 64 7 cont0 (:133)
- 124 H TFFE + t 0 0 0 0 7 64 2 data2 (:134)
- 114 H TFFE + t 0 0 0 0 5 64 2 data1 (:135)
(83) 123 H TFFE + t 0 0 0 0 7 64 3 data0 (:136)
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