rz_msmg.vhd

米字型数码管的编码方法。自动循环显示至少四个以上单词。

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity select_word is
port( clk : in std_logic;
      X1,X2,X3,X4 : out std_logic_vector(15 downto 0));
end entity select_word;

architecture art of select_word is
  signal data : std_logic_vector(2 downto 0);
  begin
  process (clk) is
    begin
    if clk'event and clk='1' then
       if data = "100" then
          data <= "000";
       else
          data <= data + "001";
       end if;
    case data is
	 when "000" => x1<=X"0000"; x2<=X"4a00"; x3<=X"0acc"; x4<=X"0000";  --" MY "
	 when "001" => x1<=X"11f3"; x2<=X"0acc"; x3<=X"11cf"; x4<=X"22cc";  --"NAME"
	 when "010" => x1<=X"0000"; x2<=X"11bb"; x3<=X"4433"; x4<=X"0000";  --" IS "
	 when "011" => x1<=X"22cc"; x2<=X"11cf"; x3<=X"31c7"; x4<=X"0000"; --" RAN"
     when "100" => x1<=X"22cc"; x2<=X"11f3"; x3<=X"11cc"; x4<=X"8833"; --"ZHEN"
     when others => null;
    end case;
    end if;
    end process;
end architecture art;
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity selects is
port(clk : in std_logic;
     X1,X2,X3,X4 : in std_logic_vector(15 downto 0);
     sele : out std_logic_vector(3 downto 0);
     outp : out std_logic_vector(15 downto 0));
end entity selects;

architecture art of selects is
  signal data : std_logic_vector(3 downto 0);
  signal cont : std_logic_vector(3 downto 0);
  signal num : std_logic_vector(1 downto 0);
  begin
  process (clk) is
    begin
    if (clk'event and clk = '1') then
        if data = "0000" then
           data <= "1110";
        else
           data <= data(2 downto 0) & data(3);
           sele <= data;
       end if;
       if cont = "0000" then
          cont <= "1111";
          if num = "11" then
             num <= "00";
             outp <= X4;
          else
          case num is
              when "00" => outp <= X1;
              when "01" => outp <= X2;
              when "10" => outp <= X3;
              when "11" => outp <= X4;
              when others => null;
          end case;
          num <= num + 1;
          end if;
       else
           cont <= cont - 1;
       end if;
    end if;
  end process;
end architecture art;
--------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity rz_msmg is
port(clk : in std_logic;
     sele : out std_logic_vector(3 downto 0);
     outp : out std_logic_vector(15 downto 0));
end entity rz_msmg;

architecture art of rz_msmg is
  
  component select_word is
  port( clk : in std_logic;
      X1,X2,X3,X4 : out std_logic_vector(15 downto 0));
  end component select_word;

  component selects is
  port(clk : in std_logic;
     X1,X2,X3,X4 : in std_logic_vector(15 downto 0);
     sele : out std_logic_vector(3 downto 0);
     outp : out std_logic_vector(15 downto 0));
  end component selects;

  signal X,Y,M,N : std_logic_vector(15 downto 0);
  begin
    U0: select_word port map(clk=>clK,X1=>X,X2=>Y,X3=>M,X4=>N);
    U1: selects port map(clk=>clk,X1=>X,X2=>Y,X3=>M,X4=>N,sele=>sele,outp=>outp);
end architecture art;