class.ptf

fpga嵌入式系统组件

                  title = "Parameters";
                  layout = "form";
                  align = "left";
                  EDIT e1
                  {
                     id = "CLK_FREQ";
                     editable = "1";
                     title = "CLK_FREQ:";
                     columns = "40";
                     tooltip = "default value: 32'b00000010111110101111000010000000";
                     DATA 
                     {
                        $H/clk_freq = "$";
                     }
                     q = "'";
                     warning = "{{ if(!(regexp('ugly_'+$H/clk_freq,'ugly_[0-9]*'+$q+'[bB][01][_01]*')||regexp('ugly_'+$H/clk_freq,'ugly_[0-9]*'+$q+'[hH][0-9a-fA-F][_0-9a-fA-F]*')||regexp('ugly_'+$H/clk_freq,'ugly_[0-9]*'+$q+'[oO][0-7][_0-7]*')||regexp('ugly_'+$H/clk_freq,'ugly_0x[0-9a-fA-F]+')||regexp('ugly_'+$H/clk_freq,'ugly_-?[0-9]+')))'CLK_FREQ must be numeric constant, not '+$H/clk_freq; }}";
                  }
                  EDIT e2
                  {
                     id = "DCLK_FREQ";
                     editable = "1";
                     title = "DCLK_FREQ:";
                     columns = "40";
                     tooltip = "default value: 32'b00000000000100100100111110000000";
                     DATA 
                     {
                        $H/dclk_freq = "$";
                     }
                     q = "'";
                     warning = "{{ if(!(regexp('ugly_'+$H/dclk_freq,'ugly_[0-9]*'+$q+'[bB][01][_01]*')||regexp('ugly_'+$H/dclk_freq,'ugly_[0-9]*'+$q+'[hH][0-9a-fA-F][_0-9a-fA-F]*')||regexp('ugly_'+$H/dclk_freq,'ugly_[0-9]*'+$q+'[oO][0-7][_0-7]*')||regexp('ugly_'+$H/dclk_freq,'ugly_0x[0-9a-fA-F]+')||regexp('ugly_'+$H/dclk_freq,'ugly_-?[0-9]+')))'DCLK_FREQ must be numeric constant, not '+$H/dclk_freq; }}";
                  }
               }
            }
         }
      }
   }
   SOPC_Builder_Version = "5.10";
   COMPONENT_BUILDER 
   {
      HDL_PARAMETERS 
      {
         # generated by CBDocument.getParameterContainer
         # used only by Component Editor
         HDL_PARAMETER clk_freq
         {
            parameter_name = "CLK_FREQ";
            type = "integer";
            default_value = "32'b00000010111110101111000010000000";
            editable = "1";
            tooltip = "";
         }
         HDL_PARAMETER dclk_freq
         {
            parameter_name = "DCLK_FREQ";
            type = "integer";
            default_value = "32'b00000000000100100100111110000000";
            editable = "1";
            tooltip = "";
         }
      }
      SW_FILES 
      {
      }
      built_on = "2007.03.21.01:13:23";
      CACHED_HDL_INFO 
      {
         # cached hdl info, emitted by CBFrameRealtime.getDocumentCachedHDLInfoSection
         # used only by Component Builder
         FILE ads7822.v
         {
            file_mod = "Wed Mar 21 01:00:36 CST 2007";
            quartus_map_start = "Wed Mar 21 01:05:25 CST 2007";
            quartus_map_finished = "Wed Mar 21 01:06:09 CST 2007";
            #found 1 valid modules
            WRAPPER ads7822
            {
               CLASS ads7822
               {
                  CB_GENERATOR 
                  {
                     HDL_FILES 
                     {
                        FILE 
                        {
                           use_in_simulation = "1";
                           use_in_synthesis = "1";
                           filepath = "D:/Test/C20_BGA_ADC/ads7822.v";
                        }
                     }
                     top_module_name = "ads7822";
                     emit_system_h = "0";
                  }
                  MODULE_DEFAULTS global_signals
                  {
                     class = "ads7822";
                     class_version = "1.0";
                     SYSTEM_BUILDER_INFO 
                     {
                        Instantiate_In_System_Module = "1";
                     }
                     SLAVE avalon_slave_0
                     {
                        SYSTEM_BUILDER_INFO 
                        {
                           Bus_Type = "avalon";
                        }
                        PORT_WIRING 
                        {
                           PORT AD_DATA
                           {
                              width = "1";
                              width_expression = "";
                              direction = "input";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT AD_CS
                           {
                              width = "1";
                              width_expression = "";
                              direction = "output";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT AD_CLK
                           {
                              width = "1";
                              width_expression = "";
                              direction = "output";
                              type = "export";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT irq
                           {
                              width = "1";
                              width_expression = "";
                              direction = "output";
                              type = "irq";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT readdata
                           {
                              width = "16";
                              width_expression = "";
                              direction = "output";
                              type = "readdata";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT read_n
                           {
                              width = "1";
                              width_expression = "";
                              direction = "input";
                              type = "read_n";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                           PORT chipselect_n
                           {
                              width = "1";
                              width_expression = "";
                              direction = "input";
                              type = "chipselect_n";
                              is_shared = "0";
                              vhdl_record_name = "";
                              vhdl_record_type = "";
                           }
                        }
                     }
                     PORT_WIRING 
                     {
                        PORT clk
                        {
                           width = "1";
                           width_expression = "";
                           direction = "input";
                           type = "clk";
                           is_shared = "0";
                           vhdl_record_name = "";
                           vhdl_record_type = "";
                        }
                     }
                  }
                  USER_INTERFACE 
                  {
                     USER_LABELS 
                     {
                        name = "ads7822";
                        technology = "imported components";
                     }
                  }
                  SOPC_Builder_Version = "0.0";
                  COMPONENT_BUILDER 
                  {
                     HDL_PARAMETERS 
                     {
                        # generated by CBDocument.getParameterContainer
                        # used only by Component Editor
                        HDL_PARAMETER clk_freq
                        {
                           parameter_name = "CLK_FREQ";
                           type = "integer";
                           default_value = "32'b00000010111110101111000010000000";
                           editable = "1";
                           tooltip = "";
                        }
                        HDL_PARAMETER dclk_freq
                        {
                           parameter_name = "DCLK_FREQ";
                           type = "integer";
                           default_value = "32'b00000000000100100100111110000000";
                           editable = "1";
                           tooltip = "";
                        }
                     }
                  }
               }
            }
         }
      }
   }
   ASSOCIATED_FILES 
   {
      Add_Program = "the_wizard_ui";
      Edit_Program = "the_wizard_ui";
      Generator_Program = "cb_generator.pl";
   }
}