clock.par

这是一个用VHDL写的简易的CPU的程序

Release 6.2i Par G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.

hit58::  Wed Nov 21 16:43:43 2007


C:/Xilinx/bin/nt/par.exe -w -intstyle ise -ol std -t 1 clock_map.ncd clock.ncd
clock.pcf 


Constraints file: clock.pcf

Loading device database for application Par from file "clock_map.ncd".
   "clock" is an NCD, version 2.38, device xcv200, package pq240, speed -4
Loading device for application Par from file 'v200.nph' in environment
C:/Xilinx.
Device speed data version:  FINAL 1.123 2003-12-13.


Device utilization summary:

   Number of External IOBs             4 out of 166     2%
      Number of LOCed External IOBs    0 out of 4       0%

   Number of SLICEs                    3 out of 2352    1%




Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:98968d) REAL time: 0 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
.
Phase 5.8 (Checksum:98cd93) REAL time: 0 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 0 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs 

Writing design to file clock.ncd.

Total REAL time to Placer completion: 0 secs 
Total CPU time to Placer completion: 0 secs 


Phase 1: 11 unrouted;       REAL time: 0 secs 

Phase 2: 10 unrouted;       REAL time: 0 secs 

Phase 3: 0 unrouted;       REAL time: 0 secs 

Phase 4: 0 unrouted;       REAL time: 0 secs 

Total REAL time to Router completion: 0 secs 
Total CPU time to Router completion: 0 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|          clk_IBUF          |Low-Skew  |    2   |  0.004     |  4.440      |
+----------------------------+----------+--------+------------+-------------+
|               mt0          |   Local  |    3   |  0.000     |  1.543      |
+----------------------------+----------+--------+------------+-------------+


   The Delay Summary Report

   The SCORE FOR THIS DESIGN is: 268


The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

   The AVERAGE CONNECTION DELAY for this design is:        2.388
   The MAXIMUM PIN DELAY IS:                               4.440
   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   1.448

   Listing Pin Delays by value: (nsec)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 5.00  d >= 5.00
   ---------   ---------   ---------   ---------   ---------   ---------
           0           7           0           2           2           0

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 0 secs 
Total CPU time to PAR completion: 1 secs 

Peak Memory Usage:  53 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file clock.ncd.


PAR done.