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这是一个用VHDL写的简易的CPU的程序

u1_mt1:Q                           | NONE                   | 5     |
-----------------------------------+------------------------+-------+
(*) This 1 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 29.484ns (Maximum Frequency: 33.917MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 17.686ns
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".



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Compiling vhdl file e:/sum/sum.vhdl in Library work.
Entity <sum> (Architecture <behav>) compiled.



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Compiling vhdl file e:/sum/sum.vhdl in Library work.
Entity <sum> (Architecture <behav>) compiled.



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Compiling vhdl file e:/sum/sum.vhdl in Library work.
Entity <sum> (Architecture <behav>) compiled.



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Compiling vhdl file e:/sum/sum.vhdl in Library work.
Entity <sum> (Architecture <behav>) compiled.



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Compiling vhdl file e:/sum/sum.vhdl in Library work.
Entity <sum> (Architecture <behav>) compiled.



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Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
WARNING:HDLParsers:3215 - Unit work/MSI is now defined in a different file: was e:/sum/msi.vhdl, now is D:/sum/msi.vhdl
WARNING:HDLParsers:3215 - Unit work/MSI/MAIN is now defined in a different file: was e:/sum/msi.vhdl, now is D:/sum/msi.vhdl
WARNING:HDLParsers:3215 - Unit work/IEU is now defined in a different file: was e:/sum/ieu.vhdl, now is D:/sum/ieu.vhdl
WARNING:HDLParsers:3215 - Unit work/IEU/MAIN is now defined in a different file: was e:/sum/ieu.vhdl, now is D:/sum/ieu.vhdl
WARNING:HDLParsers:3215 - Unit work/CU is now defined in a different file: was e:/sum/cu.vhd, now is D:/sum/cu.vhd
WARNING:HDLParsers:3215 - Unit work/CU/MAIN is now defined in a different file: was e:/sum/cu.vhd, now is D:/sum/cu.vhd
WARNING:HDLParsers:3215 - Unit work/CLOCK is now defined in a different file: was e:/sum/clock.vhdl, now is D:/sum/clock.vhdl
WARNING:HDLParsers:3215 - Unit work/CLOCK/MAIN is now defined in a different file: was e:/sum/clock.vhdl, now is D:/sum/clock.vhdl
Compiling vhdl file D:/sum/clock.vhdl in Library work.
Architecture main of Entity clock is up to date.
Compiling vhdl file D:/sum/cu.vhd in Library work.
Architecture main of Entity cu is up to date.
Compiling vhdl file D:/sum/ieu.vhdl in Library work.
Architecture main of Entity ieu is up to date.
Compiling vhdl file D:/sum/msi.vhdl in Library work.
Architecture main of Entity msi is up to date.
Compiling vhdl file D:/sum/sum.vhdl in Library work.
Entity <sum> (Architecture <behav>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <sum> (Architecture <behav>).
Entity <sum> analyzed. Unit <sum> generated.

Analyzing Entity <clock> (Architecture <main>).
WARNING:Xst:819 - D:/sum/clock.vhdl line 32: The following signals are missing in the process sensitivity list:
   reset.
WARNING:Xst:819 - D:/sum/clock.vhdl line 41: The following signals are missing in the process sensitivity list:
   reset.
Entity <clock> analyzed. Unit <clock> generated.

Analyzing Entity <cu> (Architecture <main>).
INFO:Xst:1561 - D:/sum/cu.vhd line 61: Mux is complete : default of case is discarded
WARNING:Xst:819 - D:/sum/cu.vhd line 39: The following signals are missing in the process sensitivity list:
   reset.
Entity <cu> analyzed. Unit <cu> generated.

Analyzing Entity <ieu> (Architecture <main>).
INFO:Xst:1561 - D:/sum/ieu.vhdl line 32: Mux is complete : default of case is discarded
INFO:Xst:1561 - D:/sum/ieu.vhdl line 46: Mux is complete : default of case is discarded
WARNING:Xst:819 - D:/sum/ieu.vhdl line 50: The following signals are missing in the process sensitivity list:
   cri, crj.
Entity <ieu> analyzed. Unit <ieu> generated.

Analyzing Entity <msi> (Architecture <main>).
Entity <msi> analyzed. Unit <msi> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <msi>.
    Related source file is D:/sum/msi.vhdl.
Unit <msi> synthesized.


Synthesizing Unit <ieu>.
    Related source file is D:/sum/ieu.vhdl.
    Found 1-of-8 decoder for signal <sri>.
    Found 1-of-8 decoder for signal <srj>.
    Summary:
	inferred   2 Decoder(s).
Unit <ieu> synthesized.


Synthesizing Unit <cu>.
    Related source file is D:/sum/cu.vhd.
    Found 32x28-bit ROM for signal <cdata>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0008> created at line 44.
    Found 5-bit register for signal <caddress>.
    Found 1 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   1 ROM(s).
	inferred   5 D-type flip-flop(s).
	inferred   2 Multiplexer(s).
Unit <cu> synthesized.


Synthesizing Unit <clock>.
    Related source file is D:/sum/clock.vhdl.
    Found 1-bit register for signal <mstart>.
    Found 1-bit register for signal <mt0>.
    Found 1-bit register for signal <mt1>.
    Summary:
	inferred   3 D-type flip-flop(s).
Unit <clock> synthesized.


Synthesizing Unit <sum>.
    Related source file is D:/sum/sum.vhdl.
WARNING:Xst:1779 - Inout <sdata> is used but is never assigned.
WARNING:Xst:646 - Signal <writem> is assigned but never used.
    Found 16-bit adder for signal <$n0000> created at line 220.
    Found 8-bit 16-to-1 multiplexer for signal <$n0012> created at line 111.
    Found 8-bit addsub for signal <$n0089>.
    Found 8-bit register for signal <databus>.
    Found 8-bit register for signal <f1>.
    Found 8-bit register for signal <f2>.
    Found 16-bit register for signal <ir>.
    Found 16-bit register for signal <mar>.
    Found 16-bit register for signal <mdr>.
    Found 16-bit register for signal <pc>.
    Found 8-bit register for signal <reg0>.
    Found 8-bit register for signal <reg1>.
    Found 8-bit register for signal <reg2>.
    Found 8-bit register for signal <reg3>.
    Found 8-bit register for signal <reg4>.
    Found 8-bit register for signal <reg5>.
    Found 8-bit register for signal <reg6>.
    Found 8-bit register for signal <reg7>.
    Found 48 1-bit 2-to-1 multiplexers.
    Summary:
	inferred 152 D-type flip-flop(s).
	inferred   2 Adder/Subtracter(s).
	inferred  56 Multiplexer(s).
Unit <sum> synthesized.

INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# ROMs                             : 1
 32x28-bit ROM                     : 1
# Adders/Subtractors               : 2
 8-bit addsub                      : 1
 16-bit adder                      : 1
# Registers                        : 68
 1-bit register                    : 56
 16-bit register                   : 1
 8-bit register                    : 11
# Multiplexers                     : 51
 1-bit 2-to-1 multiplexer          : 49
 8-bit 16-to-1 multiplexer         : 1
 1-bit 4-to-1 multiplexer          : 1
# Decoders                         : 2
 1-of-8 decoder                    : 2

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <sum> ...

Optimizing unit <msi> ...

Optimizing unit <cu> ...

Optimizing unit <ieu> ...
Loading device for application Xst from file 'v200.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block sum, actual ratio is 8.
FlipFlop u2_caddress_0 has been replicated 1 time(s)
FlipFlop u2_caddress_1 has been replicated 1 time(s)
FlipFlop u2_caddress_3 has been replicated 1 time(s)
FlipFlop u2_caddress_2 has been replicated 1 time(s)
FlipFlop ir_11 has been replicated 1 time(s)
FlipFlop u2_caddress_4 has been replicated 1 time(s)
FlipFlop ir_12 has been replicated 1 time(s)
FlipFlop u1_mt0 has been replicated 1 ti