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这是一个用VHDL写的简易的CPU的程序

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# ROMs                             : 1
 32x28-bit ROM                     : 1
# Adders/Subtractors               : 2
 8-bit addsub                      : 1
 16-bit adder                      : 1
# Registers                        : 69
 16-bit register                   : 2
 1-bit register                    : 56
 8-bit register                    : 11
# Latches                          : 2
 1-bit latch                       : 1
 16-bit latch                      : 1
# Multiplexers                     : 35
 1-bit 2-to-1 multiplexer          : 33
 8-bit 16-to-1 multiplexer         : 1
 1-bit 4-to-1 multiplexer          : 1
# Decoders                         : 2
 1-of-8 decoder                    : 2
# Tristates                        : 1
 16-bit tristate buffer            : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:637 - Naming conflict between instance 0 of unit mdr and instance mdr_0 of unit sum : renaming mdr_0 to mdr_01.
WARNING:Xst:637 - Naming conflict between instance 1 of unit mdr and instance mdr_1 of unit sum : renaming mdr_1 to mdr_16.
WARNING:Xst:637 - Naming conflict between instance 2 of unit mdr and instance mdr_2 of unit sum : renaming mdr_2 to mdr_21.
WARNING:Xst:637 - Naming conflict between instance 3 of unit mdr and instance mdr_3 of unit sum : renaming mdr_3 to mdr_31.
WARNING:Xst:637 - Naming conflict between instance 4 of unit mdr and instance mdr_4 of unit sum : renaming mdr_4 to mdr_41.
WARNING:Xst:637 - Naming conflict between instance 5 of unit mdr and instance mdr_5 of unit sum : renaming mdr_5 to mdr_51.
WARNING:Xst:637 - Naming conflict between instance 6 of unit mdr and instance mdr_6 of unit sum : renaming mdr_6 to mdr_61.
WARNING:Xst:637 - Naming conflict between instance 7 of unit mdr and instance mdr_7 of unit sum : renaming mdr_7 to mdr_71.
WARNING:Xst:637 - Naming conflict between instance 8 of unit mdr and instance mdr_8 of unit sum : renaming mdr_8 to mdr_81.
WARNING:Xst:637 - Naming conflict between instance 9 of unit mdr and instance mdr_9 of unit sum : renaming mdr_9 to mdr_91.
WARNING:Xst:637 - Naming conflict between instance 10 of unit mdr and instance mdr_10 of unit sum : renaming mdr_10 to mdr_101.
WARNING:Xst:637 - Naming conflict between instance 11 of unit mdr and instance mdr_11 of unit sum : renaming mdr_11 to mdr_111.
WARNING:Xst:637 - Naming conflict between instance 12 of unit mdr and instance mdr_12 of unit sum : renaming mdr_12 to mdr_121.
WARNING:Xst:637 - Naming conflict between instance 13 of unit mdr and instance mdr_13 of unit sum : renaming mdr_13 to mdr_131.
WARNING:Xst:637 - Naming conflict between instance 14 of unit mdr and instance mdr_14 of unit sum : renaming mdr_14 to mdr_141.
WARNING:Xst:637 - Naming conflict between instance 15 of unit mdr and instance mdr_15 of unit sum : renaming mdr_15 to mdr_151.
WARNING:Xst:528 - Multi-source in Unit <sum> on signal <mdr_131> not replaced by logic
Sources are: mdr_13:Q, mdr_131:Q
WARNING:Xst:528 - Multi-source in Unit <sum> on signal <mdr_101> not replaced by logic
Sources are: mdr_10:Q, mdr_101:Q
WARNING:Xst:528 - Multi-source in Unit <sum> on signal <mdr_71> not replaced by logic
Sources are: mdr_7:Q, mdr_71:Q
WARNING:Xst:528 - Multi-source in Unit <sum> on signal <mdr_41> not replaced by logic
Sources are: mdr_4:Q, mdr_41:Q
WARNING:Xst:528 - Multi-source in Unit <sum> on signal <mdr_16> not replaced by logic
Sources are: mdr_1:Q, mdr_16:Q
WARNING:Xst:528 - Multi-source in Unit <sum> on signal <mdr_151> not replaced by logic
Sources are: mdr_15:Q, mdr_151:Q
WARNING:Xst:528 - Multi-source in Unit <sum> on signal <mdr_121> not replaced by logic
Sources are: mdr_12:Q, mdr_121:Q
WARNING:Xst:528 - Multi-source in Unit <sum> on signal <mdr_21> not replaced by logic
Sources are: mdr_2:Q, mdr_21:Q
WARNING:Xst:528 - Multi-source in Unit <sum> on signal <mdr_51> not replaced by logic
Sources are: mdr_5:Q, mdr_51:Q
WARNING:Xst:528 - Multi-source in Unit <sum> on signal <mdr_31> not replaced by logic
Sources are: mdr_3:Q, mdr_31:Q
WARNING:Xst:528 - Multi-source in Unit <sum> on signal <mdr_81> not replaced by logic
Sources are: mdr_8:Q, mdr_81:Q
WARNING:Xst:528 - Multi-source in Unit <sum> on signal <mdr_61> not replaced by logic
Sources are: mdr_6:Q, mdr_61:Q
WARNING:Xst:528 - Multi-source in Unit <sum> on signal <mdr_111> not replaced by logic
Sources are: mdr_11:Q, mdr_111:Q
WARNING:Xst:528 - Multi-source in Unit <sum> on signal <mdr_141> not replaced by logic
Sources are: mdr_14:Q, mdr_141:Q
WARNING:Xst:528 - Multi-source in Unit <sum> on signal <mdr_01> not replaced by logic
Sources are: mdr_0:Q, mdr_01:Q
WARNING:Xst:528 - Multi-source in Unit <sum> on signal <mdr_91> not replaced by logic
Sources are: mdr_9:Q, mdr_91:Q
ERROR:Xst:415 - Synthesis failed
CPU : 2.25 / 3.19 s | Elapsed : 2.00 / 3.00 s
 
--> 

Total memory usage is 55432 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file e:/sum/clock.vhdl in Library work.
Architecture main of Entity clock is up to date.
Compiling vhdl file e:/sum/cu.vhd in Library work.
Architecture main of Entity cu is up to date.
Compiling vhdl file e:/sum/ieu.vhdl in Library work.
Architecture main of Entity ieu is up to date.
Compiling vhdl file e:/sum/msi.vhdl in Library work.
Architecture main of Entity msi is up to date.
Compiling vhdl file e:/sum/sum.vhdl in Library work.
Entity <sum> (Architecture <behav>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <sum> (Architecture <behav>).
Entity <sum> analyzed. Unit <sum> generated.

Analyzing Entity <clock> (Architecture <main>).
WARNING:Xst:819 - e:/sum/clock.vhdl line 32: The following signals are missing in the process sensitivity list:
   reset.
WARNING:Xst:819 - e:/sum/clock.vhdl line 41: The following signals are missing in the process sensitivity list:
   reset.
Entity <clock> analyzed. Unit <clock> generated.

Analyzing Entity <cu> (Architecture <main>).
INFO:Xst:1561 - e:/sum/cu.vhd line 61: Mux is complete : default of case is discarded
WARNING:Xst:819 - e:/sum/cu.vhd line 39: The following signals are missing in the process sensitivity list:
   reset.
Entity <cu> analyzed. Unit <cu> generated.

Analyzing Entity <ieu> (Architecture <main>).
INFO:Xst:1561 - e:/sum/ieu.vhdl line 32: Mux is complete : default of case is discarded
INFO:Xst:1561 - e:/sum/ieu.vhdl line 46: Mux is complete : default of case is discarded
WARNING:Xst:819 - e:/sum/ieu.vhdl line 50: The following signals are missing in the process sensitivity list:
   cri, crj.
Entity <ieu> analyzed. Unit <ieu> generated.

Analyzing Entity <msi> (Architecture <main>).
Entity <msi> analyzed. Unit <msi> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <msi>.
    Related source file is e:/sum/msi.vhdl.
Unit <msi> synthesized.


Synthesizing Unit <ieu>.
    Related source file is e:/sum/ieu.vhdl.
    Found 1-of-8 decoder for signal <sri>.
    Found 1-of-8 decoder for signal <srj>.
    Summary:
	inferred   2 Decoder(s).
Unit <ieu> synthesized.


Synthesizing Unit <cu>.
    Related source file is e:/sum/cu.vhd.
    Found 32x28-bit ROM for signal <cdata>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0008> created at line 44.
    Found 5-bit register for signal <caddress>.
    Found 1 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   1 ROM(s).
	inferred   5 D-type flip-flop(s).
	inferred   2 Multiplexer(s).
Unit <cu> synthesized.


Synthesizing Unit <clock>.
    Related source file is e:/sum/clock.vhdl.
    Found 1-bit register for signal <mstart>.
    Found 1-bit register for signal <mt0>.
    Found 1-bit register for signal <mt1>.
    Summary:
	inferred   3 D-type flip-flop(s).
Unit <clock> synthesized.


Synthesizing Unit <sum>.
    Related source file is e:/sum/sum.vhdl.
WARNING:Xst:736 - Found 16-bit latch for signal <Mtridata_sdata> created at line 248.
WARNING:Xst:736 - Found 1-bit latch for signal <Mtrien_sdata> created at line 248.
    Found 16-bit tristate buffer for signal <sdata>.
    Found 16-bit adder for signal <$n0000> created at line 220.
    Found 8-bit 16-to-1 multiplexer for signal <$n0013> created at line 111.
    Found 8-bit addsub for signal <$n0095>.
    Found 8-bit register for signal <databus>.
    Found 8-bit register for signal <f1>.
    Found 8-bit register for signal <f2>.
    Found 16-bit register for signal <ir>.
    Found 16-bit register for signal <mar>.
    Found 16-bit register for signal <mdr>.
    Found 16-bit register for signal <pc>.
    Found 8-bit register for signal <reg0>.
    Found 8-bit register for signal <reg1>.
    Found 8-bit register for signal <reg2>.
    Found 8-bit register for signal <reg3>.
    Found 8-bit register for signal <reg4>.
    Found 8-bit register for signal <reg5>.
    Found 8-bit register for signal <reg6>.
    Found 8-bit register for signal <reg7>.
    Found 48 1-bit 2-to-1 multiplexers.
    Summary:
	inferred 152 D-type flip-flop(s).
	inferred   2 Adder/Subtracter(s).
	inferred  56 Multiplexer(s).
	inferred  16 Tristate(s).
Unit <sum> synthesized.

INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# ROMs                             : 1
 32x28-bit ROM                     : 1
# Adders/Subtractors               : 2
 8-bit addsub                      : 1
 16-bit adder                      : 1
# Registers                        : 68
 1-bit register                    : 56
 16-bit register                   : 1
 8-bit register                    : 11
# Latches                          : 2
 1-bit latch                       : 1
 16-bit latch                      : 1
# Multiplexers                     : 51
 1-bit 2-to-1 multiplexer          : 49
 8-bit 16-to-1 multiplexer         : 1
 1-bit 4-to-1 multiplexer          : 1
# Decoders                         : 2
 1-of-8 decoder                    : 2
# Tristates                        : 1
 16-bit tristate buffer            : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <sum> ...

Optimizing unit <msi> ...

Optimizing unit <cu> ...

Optimizing unit <ieu> ...
Loading device for application Xst from file 'v200.nph' in environment D:/hardware/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block sum, actual ratio is 9.
FlipFlop ir_11 has been replicated 1 time(s)
FlipFlop ir_12 has been replicated 1 time(s)
FlipFlop u1_mt0 has been replicated 1 time(s)
Latch Mtrien_sdata has been replicated 15 time(s) to handle iob=true attribute.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : v200pq240-4 

 Number of Slices:                     183  out of   2352     7%  
 Number of Slice Flip Flops:           195  out of   4704     4%  
 Number of 4 input LUTs:               294  out of   4704     6%  
 Number of bonded IOBs:                 38  out of    170    22%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
u1_mt0_1:Q                         | NONE                   | 84    |
u1_mt0:Q                           | NONE                   | 87    |
_n0248(_n02481:O)                  | NONE(*)(Mtrien_sdata_14)| 16    |
clk                                | BUFGP                  | 3     |