__projnav.log

这是一个用VHDL写的简易的CPU的程序

ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file e:/sum/clock.vhdl in Library work.
Architecture main of Entity clock is up to date.
Compiling vhdl file e:/sum/cu.vhd in Library work.
Architecture main of Entity cu is up to date.
Compiling vhdl file e:/sum/ieu.vhdl in Library work.
Architecture main of Entity ieu is up to date.
Compiling vhdl file e:/sum/msi.vhdl in Library work.
Architecture main of Entity msi is up to date.
Compiling vhdl file e:/sum/sum.vhdl in Library work.
Entity <sum> (Architecture <behav>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <sum> (Architecture <behav>).
ERROR:Xst:827 - e:/sum/sum.vhdl line 253: Signal mdr<7> cannot be synthesized, bad synchronous description.
--> 

Total memory usage is 49288 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file e:/sum/clock.vhdl in Library work.
Architecture main of Entity clock is up to date.
Compiling vhdl file e:/sum/cu.vhd in Library work.
Architecture main of Entity cu is up to date.
Compiling vhdl file e:/sum/ieu.vhdl in Library work.
Architecture main of Entity ieu is up to date.
Compiling vhdl file e:/sum/msi.vhdl in Library work.
Architecture main of Entity msi is up to date.
Compiling vhdl file e:/sum/sum.vhdl in Library work.
Entity <sum> (Architecture <behav>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <sum> (Architecture <behav>).
ERROR:Xst:827 - e:/sum/sum.vhdl line 253: Signal mdr<7> cannot be synthesized, bad synchronous description.
--> 

Total memory usage is 49288 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file e:/sum/clock.vhdl in Library work.
Architecture main of Entity clock is up to date.
Compiling vhdl file e:/sum/cu.vhd in Library work.
Architecture main of Entity cu is up to date.
Compiling vhdl file e:/sum/ieu.vhdl in Library work.
Architecture main of Entity ieu is up to date.
Compiling vhdl file e:/sum/msi.vhdl in Library work.
Architecture main of Entity msi is up to date.
Compiling vhdl file e:/sum/sum.vhdl in Library work.
Entity <sum> (Architecture <behav>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <sum> (Architecture <behav>).
WARNING:Xst:819 - e:/sum/sum.vhdl line 245: The following signals are missing in the process sensitivity list:
   mdr.
ERROR:Xst:827 - e:/sum/sum.vhdl line 253: Signal mdr<7> cannot be synthesized, bad synchronous description.
--> 

Total memory usage is 49288 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file e:/sum/clock.vhdl in Library work.
Architecture main of Entity clock is up to date.
Compiling vhdl file e:/sum/cu.vhd in Library work.
Architecture main of Entity cu is up to date.
Compiling vhdl file e:/sum/ieu.vhdl in Library work.
Architecture main of Entity ieu is up to date.
Compiling vhdl file e:/sum/msi.vhdl in Library work.
Architecture main of Entity msi is up to date.
Compiling vhdl file e:/sum/sum.vhdl in Library work.
Entity <sum> (Architecture <behav>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <sum> (Architecture <behav>).
ERROR:Xst:827 - e:/sum/sum.vhdl line 253: Signal mdr<7> cannot be synthesized, bad synchronous description.
--> 

Total memory usage is 49288 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file e:/sum/clock.vhdl in Library work.
Architecture main of Entity clock is up to date.
Compiling vhdl file e:/sum/cu.vhd in Library work.
Architecture main of Entity cu is up to date.
Compiling vhdl file e:/sum/ieu.vhdl in Library work.
Architecture main of Entity ieu is up to date.
Compiling vhdl file e:/sum/msi.vhdl in Library work.
Architecture main of Entity msi is up to date.
Compiling vhdl file e:/sum/sum.vhdl in Library work.
ERROR:HDLParsers:164 - e:/sum/sum.vhdl Line 265. parse error, unexpected IF, expecting PROCESS
--> 

Total memory usage is 49288 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file e:/sum/clock.vhdl in Library work.
Architecture main of Entity clock is up to date.
Compiling vhdl file e:/sum/cu.vhd in Library work.
Architecture main of Entity cu is up to date.
Compiling vhdl file e:/sum/ieu.vhdl in Library work.
Architecture main of Entity ieu is up to date.
Compiling vhdl file e:/sum/msi.vhdl in Library work.
Architecture main of Entity msi is up to date.
Compiling vhdl file e:/sum/sum.vhdl in Library work.
Entity <sum> (Architecture <behav>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <sum> (Architecture <behav>).
Entity <sum> analyzed. Unit <sum> generated.

Analyzing Entity <clock> (Architecture <main>).
WARNING:Xst:819 - e:/sum/clock.vhdl line 32: The following signals are missing in the process sensitivity list:
   reset.
WARNING:Xst:819 - e:/sum/clock.vhdl line 41: The following signals are missing in the process sensitivity list:
   reset.
Entity <clock> analyzed. Unit <clock> generated.

Analyzing Entity <cu> (Architecture <main>).
INFO:Xst:1561 - e:/sum/cu.vhd line 61: Mux is complete : default of case is discarded
WARNING:Xst:819 - e:/sum/cu.vhd line 39: The following signals are missing in the process sensitivity list:
   reset.
Entity <cu> analyzed. Unit <cu> generated.

Analyzing Entity <ieu> (Architecture <main>).
INFO:Xst:1561 - e:/sum/ieu.vhdl line 32: Mux is complete : default of case is discarded
INFO:Xst:1561 - e:/sum/ieu.vhdl line 46: Mux is complete : default of case is discarded
WARNING:Xst:819 - e:/sum/ieu.vhdl line 50: The following signals are missing in the process sensitivity list:
   cri, crj.
Entity <ieu> analyzed. Unit <ieu> generated.

Analyzing Entity <msi> (Architecture <main>).
Entity <msi> analyzed. Unit <msi> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <msi>.
    Related source file is e:/sum/msi.vhdl.
Unit <msi> synthesized.


Synthesizing Unit <ieu>.
    Related source file is e:/sum/ieu.vhdl.
    Found 1-of-8 decoder for signal <sri>.
    Found 1-of-8 decoder for signal <srj>.
    Summary:
	inferred   2 Decoder(s).
Unit <ieu> synthesized.


Synthesizing Unit <cu>.
    Related source file is e:/sum/cu.vhd.
    Found 32x28-bit ROM for signal <cdata>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0008> created at line 44.
    Found 5-bit register for signal <caddress>.
    Found 1 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   1 ROM(s).
	inferred   5 D-type flip-flop(s).
	inferred   2 Multiplexer(s).
Unit <cu> synthesized.


Synthesizing Unit <clock>.
    Related source file is e:/sum/clock.vhdl.
    Found 1-bit register for signal <mstart>.
    Found 1-bit register for signal <mt0>.
    Found 1-bit register for signal <mt1>.
    Summary:
	inferred   3 D-type flip-flop(s).
Unit <clock> synthesized.


Synthesizing Unit <sum>.
    Related source file is e:/sum/sum.vhdl.
WARNING:Xst:736 - Found 16-bit latch for signal <Mtridata_sdata> created at line 248.
WARNING:Xst:736 - Found 1-bit latch for signal <Mtrien_sdata> created at line 248.
    Found 16-bit tristate buffer for signal <sdata>.
    Found 16-bit adder for signal <$n0000> created at line 220.
    Found 8-bit 16-to-1 multiplexer for signal <$n0013> created at line 111.
    Found 8-bit addsub for signal <$n0078>.
    Found 8-bit register for signal <databus>.
    Found 8-bit register for signal <f1>.
    Found 8-bit register for signal <f2>.
    Found 16-bit register for signal <ir>.
    Found 16-bit register for signal <mar>.
    Found 16-bit register for signal <mdr>.
    Found 16-bit register for signal <pc>.
    Found 8-bit register for signal <reg0>.
    Found 8-bit register for signal <reg1>.
    Found 8-bit register for signal <reg2>.
    Found 8-bit register for signal <reg3>.
    Found 8-bit register for signal <reg4>.
    Found 8-bit register for signal <reg5>.
    Found 8-bit register for signal <reg6>.
    Found 8-bit register for signal <reg7>.
    Found 32 1-bit 2-to-1 multiplexers.
    Summary:
	inferred 168 D-type flip-flop(s).
	inferred   2 Adder/Subtracter(s).
	inferred  40 Multiplexer(s).
	inferred  16 Tristate(s).
Unit <sum> synthesized.

INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.