__projnav.log

这是一个用VHDL写的简易的CPU的程序

WARNING:Xst:528 - Multi-source in Unit <sum> on signal <sdata_13> not replaced by logic
Sources are: I68_2:O, sdata_13:Q
WARNING:Xst:528 - Multi-source in Unit <sum> on signal <sdata_14> not replaced by logic
Sources are: I68_1:O, sdata_14:Q
WARNING:Xst:528 - Multi-source in Unit <sum> on signal <sdata_15> not replaced by logic
Sources are: I68_0:O, sdata_15:Q
WARNING:Xst:528 - Multi-source in Unit <sum> on signal <sdata_0> not replaced by logic
Sources are: I68_15:O, sdata_0:Q
WARNING:Xst:528 - Multi-source in Unit <sum> on signal <sdata_1> not replaced by logic
Sources are: I68_14:O, sdata_1:Q
WARNING:Xst:528 - Multi-source in Unit <sum> on signal <sdata_2> not replaced by logic
Sources are: I68_13:O, sdata_2:Q
WARNING:Xst:528 - Multi-source in Unit <sum> on signal <sdata_3> not replaced by logic
Sources are: I68_12:O, sdata_3:Q
WARNING:Xst:528 - Multi-source in Unit <sum> on signal <mar_151> not replaced by logic
Sources are: mar_15:Q, mar_151:Q
WARNING:Xst:528 - Multi-source in Unit <sum> on signal <mar_141> not replaced by logic
Sources are: mar_14:Q, mar_141:Q
WARNING:Xst:528 - Multi-source in Unit <sum> on signal <mar_131> not replaced by logic
Sources are: mar_13:Q, mar_131:Q
WARNING:Xst:528 - Multi-source in Unit <sum> on signal <mar_121> not replaced by logic
Sources are: mar_12:Q, mar_121:Q
WARNING:Xst:528 - Multi-source in Unit <sum> on signal <mar_111> not replaced by logic
Sources are: mar_11:Q, mar_111:Q
WARNING:Xst:528 - Multi-source in Unit <sum> on signal <mar_101> not replaced by logic
Sources are: mar_10:Q, mar_101:Q
WARNING:Xst:528 - Multi-source in Unit <sum> on signal <mar_91> not replaced by logic
Sources are: mar_9:Q, mar_91:Q
WARNING:Xst:528 - Multi-source in Unit <sum> on signal <mar_81> not replaced by logic
Sources are: mar_8:Q, mar_81:Q
WARNING:Xst:528 - Multi-source in Unit <sum> on signal <mar_71> not replaced by logic
Sources are: mar_7:Q, mar_71:Q
WARNING:Xst:528 - Multi-source in Unit <sum> on signal <mar_61> not replaced by logic
Sources are: mar_6:Q, mar_61:Q
WARNING:Xst:528 - Multi-source in Unit <sum> on signal <mar_51> not replaced by logic
Sources are: mar_5:Q, mar_51:Q
WARNING:Xst:528 - Multi-source in Unit <sum> on signal <mar_41> not replaced by logic
Sources are: mar_4:Q, mar_41:Q
WARNING:Xst:528 - Multi-source in Unit <sum> on signal <mar_31> not replaced by logic
Sources are: mar_3:Q, mar_31:Q
WARNING:Xst:528 - Multi-source in Unit <sum> on signal <mar_21> not replaced by logic
Sources are: mar_2:Q, mar_21:Q
WARNING:Xst:528 - Multi-source in Unit <sum> on signal <mar_16> not replaced by logic
Sources are: mar_1:Q, mar_16:Q
WARNING:Xst:528 - Multi-source in Unit <sum> on signal <mar_01> not replaced by logic
Sources are: mar_0:Q, mar_01:Q
WARNING:Xst:528 - Multi-source in Unit <sum> on signal <pc_51> not replaced by logic
Sources are: pc_5:Q, pc_51:Q
WARNING:Xst:528 - Multi-source in Unit <sum> on signal <pc_31> not replaced by logic
Sources are: pc_3:Q, pc_31:Q
WARNING:Xst:528 - Multi-source in Unit <sum> on signal <pc_16> not replaced by logic
Sources are: pc_1:Q, pc_16:Q
WARNING:Xst:528 - Multi-source in Unit <sum> on signal <pc_61> not replaced by logic
Sources are: pc_6:Q, pc_61:Q
WARNING:Xst:528 - Multi-source in Unit <sum> on signal <pc_41> not replaced by logic
Sources are: pc_4:Q, pc_41:Q
WARNING:Xst:528 - Multi-source in Unit <sum> on signal <pc_21> not replaced by logic
Sources are: pc_2:Q, pc_21:Q
WARNING:Xst:528 - Multi-source in Unit <sum> on signal <pc_01> not replaced by logic
Sources are: pc_0:Q, pc_01:Q
WARNING:Xst:528 - Multi-source in Unit <sum> on signal <pc_151> not replaced by logic
Sources are: pc_15:Q, _n0129:_n0129, pc_151:Q
Signal is stuck at GND
WARNING:Xst:528 - Multi-source in Unit <sum> on signal <pc_141> not replaced by logic
Sources are: pc_14:Q, _n0130:_n0130, pc_141:Q
Signal is stuck at GND
WARNING:Xst:528 - Multi-source in Unit <sum> on signal <pc_131> not replaced by logic
Sources are: pc_13:Q, _n0131:_n0131, pc_131:Q
Signal is stuck at GND
WARNING:Xst:528 - Multi-source in Unit <sum> on signal <pc_121> not replaced by logic
Sources are: pc_12:Q, _n0132:_n0132, pc_121:Q
Signal is stuck at GND
WARNING:Xst:528 - Multi-source in Unit <sum> on signal <pc_111> not replaced by logic
Sources are: pc_11:Q, _n0133:_n0133, pc_111:Q
Signal is stuck at GND
WARNING:Xst:528 - Multi-source in Unit <sum> on signal <pc_101> not replaced by logic
Sources are: pc_10:Q, _n0134:_n0134, pc_101:Q
Signal is stuck at GND
WARNING:Xst:528 - Multi-source in Unit <sum> on signal <pc_91> not replaced by logic
Sources are: pc_9:Q, _n0135:_n0135, pc_91:Q
Signal is stuck at GND
WARNING:Xst:528 - Multi-source in Unit <sum> on signal <pc_81> not replaced by logic
Sources are: pc_8:Q, _n0136:_n0136, pc_81:Q
Signal is stuck at GND
WARNING:Xst:528 - Multi-source in Unit <sum> on signal <pc_71> not replaced by logic
Sources are: pc_7:Q, pc_71:Q
ERROR:Xst:415 - Synthesis failed
CPU : 2.38 / 3.30 s | Elapsed : 2.00 / 3.00 s
 
--> 

Total memory usage is 55432 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
WARNING:HDLParsers:3458 - Because of erroneous VHDL in VHDL file e:\sum/sum.vhdl, automatic determination of correct order of compilation of files in project file sum_vhdl.prj is not possible. Please compile your vhdl file(s) individually to find and fix the error(s) in your vhdl file(s). Defaulting to compilation in the order vhdl file names appear in the project file.
Compiling vhdl file e:\sum/clock.vhdl in Library work.
Architecture main of Entity clock is up to date.
Compiling vhdl file e:\sum/cu.vhd in Library work.
Architecture main of Entity cu is up to date.
Compiling vhdl file e:\sum/ieu.vhdl in Library work.
Architecture main of Entity ieu is up to date.
Compiling vhdl file e:\sum/msi.vhdl in Library work.
Architecture main of Entity msi is up to date.
Compiling vhdl file e:\sum/sum.vhdl in Library work.
ERROR:HDLParsers:164 - e:\sum/sum.vhdl Line 223. parse error, unexpected ELSE, expecting WHEN or END
--> 

Total memory usage is 49288 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file e:/sum/clock.vhdl in Library work.
Architecture main of Entity clock is up to date.
Compiling vhdl file e:/sum/cu.vhd in Library work.
Architecture main of Entity cu is up to date.
Compiling vhdl file e:/sum/ieu.vhdl in Library work.
Architecture main of Entity ieu is up to date.
Compiling vhdl file e:/sum/msi.vhdl in Library work.
Architecture main of Entity msi is up to date.
Compiling vhdl file e:/sum/sum.vhdl in Library work.
Entity <sum> (Architecture <behav>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <sum> (Architecture <behav>).
ERROR:Xst:827 - e:/sum/sum.vhdl line 272: Signal mdr<7> cannot be synthesized, bad synchronous description.
--> 

Total memory usage is 49288 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file e:/sum/clock.vhdl in Library work.
Architecture main of Entity clock is up to date.
Compiling vhdl file e:/sum/cu.vhd in Library work.
Architecture main of Entity cu is up to date.
Compiling vhdl file e:/sum/ieu.vhdl in Library work.
Architecture main of Entity ieu is up to date.
Compiling vhdl file e:/sum/msi.vhdl in Library work.
Architecture main of Entity msi is up to date.
Compiling vhdl file e:/sum/sum.vhdl in Library work.
Entity <sum> (Architecture <behav>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <sum> (Architecture <behav>).
ERROR:Xst:827 - e:/sum/sum.vhdl line 253: Signal mdr<7> cannot be synthesized, bad synchronous description.
--> 

Total memory usage is 49288 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file e:/sum/clock.vhdl in Library work.
Architecture main of Entity clock is up to date.
Compiling vhdl file e:/sum/cu.vhd in Library work.
Architecture main of Entity cu is up to date.
Compiling vhdl file e:/sum/ieu.vhdl in Library work.
Architecture main of Entity ieu is up to date.
Compiling vhdl file e:/sum/msi.vhdl in Library work.
Architecture main of Entity msi is up to date.
Compiling vhdl file e:/sum/sum.vhdl in Library work.
Entity <sum> (Architecture <behav>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <sum> (Architecture <behav>).
ERROR:Xst:827 - e:/sum/sum.vhdl line 253: Signal mdr<7> cannot be synthesized, bad synchronous description.
--> 

Total memory usage is 49288 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file e:/sum/clock.vhdl in Library work.
Architecture main of Entity clock is up to date.
Compiling vhdl file e:/sum/cu.vhd in Library work.
Architecture main of Entity cu is up to date.
Compiling vhdl file e:/sum/ieu.vhdl in Library work.
Architecture main of Entity ieu is up to date.
Compiling vhdl file e:/sum/msi.vhdl in Library work.
Architecture main of Entity msi is up to date.
Compiling vhdl file e:/sum/sum.vhdl in Library work.
Entity <sum> (Architecture <behav>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <sum> (Architecture <behav>).
ERROR:Xst:827 - e:/sum/sum.vhdl line 253: Signal mdr<7> cannot be synthesized, bad synchronous description.
--> 

Total memory usage is 49288 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file e:/sum/clock.vhdl in Library work.
Architecture main of Entity clock is up to date.
Compiling vhdl file e:/sum/cu.vhd in Library work.
Architecture main of Entity cu is up to date.
Compiling vhdl file e:/sum/ieu.vhdl in Library work.
Architecture main of Entity ieu is up to date.
Compiling vhdl file e:/sum/msi.vhdl in Library work.
Architecture main of Entity msi is up to date.
Compiling vhdl file e:/sum/sum.vhdl in Library work.
Entity <sum> (Architecture <behav>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <sum> (Architecture <behav>).
ERROR:Xst:827 - e:/sum/sum.vhdl line 253: Signal mdr<7> cannot be synthesized, bad synchronous description.
--> 

Total memory usage is 49288 kilobytes