__projnav.log

这是一个用VHDL写的简易的CPU的程序

Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
WARNING:HDLParsers:3458 - Because of erroneous VHDL in VHDL file e:\sum/sum.vhdl, automatic determination of correct order of compilation of files in project file sum_vhdl.prj is not possible. Please compile your vhdl file(s) individually to find and fix the error(s) in your vhdl file(s). Defaulting to compilation in the order vhdl file names appear in the project file.
Compiling vhdl file e:\sum/sum.vhdl in Library work.
ERROR:HDLParsers:164 - e:\sum/sum.vhdl Line 39. parse error, unexpected ENTITY
--> 

Total memory usage is 48264 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
WARNING:HDLParsers:3458 - Because of erroneous VHDL in VHDL file e:\sum/sum.vhdl, automatic determination of correct order of compilation of files in project file sum_vhdl.prj is not possible. Please compile your vhdl file(s) individually to find and fix the error(s) in your vhdl file(s). Defaulting to compilation in the order vhdl file names appear in the project file.
Compiling vhdl file e:\sum/clock.vhdl in Library work.
Entity <clock> (Architecture <main>) compiled.
Compiling vhdl file e:\sum/cu.vhd in Library work.
Entity <cu> (Architecture <main>) compiled.
Compiling vhdl file e:\sum/msi.vhdl in Library work.
Entity <msi> (Architecture <main>) compiled.
Compiling vhdl file e:\sum/sum.vhdl in Library work.
ERROR:HDLParsers:164 - e:\sum/sum.vhdl Line 125. parse error, unexpected IF, expecting CASE
--> 

Total memory usage is 49288 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
WARNING:HDLParsers:3458 - Because of erroneous VHDL in VHDL file e:\sum/sum.vhdl, automatic determination of correct order of compilation of files in project file sum_vhdl.prj is not possible. Please compile your vhdl file(s) individually to find and fix the error(s) in your vhdl file(s). Defaulting to compilation in the order vhdl file names appear in the project file.
Compiling vhdl file e:\sum/clock.vhdl in Library work.
Architecture main of Entity clock is up to date.
Compiling vhdl file e:\sum/cu.vhd in Library work.
Architecture main of Entity cu is up to date.
Compiling vhdl file e:\sum/ieu.vhdl in Library work.
Entity <ieu> (Architecture <main>) compiled.
Compiling vhdl file e:\sum/msi.vhdl in Library work.
Architecture main of Entity msi is up to date.
Compiling vhdl file e:\sum/sum.vhdl in Library work.
ERROR:HDLParsers:164 - e:\sum/sum.vhdl Line 125. parse error, unexpected IF, expecting CASE
--> 

Total memory usage is 49288 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file e:/sum/clock.vhdl in Library work.
Architecture main of Entity clock is up to date.
Compiling vhdl file e:/sum/cu.vhd in Library work.
Architecture main of Entity cu is up to date.
Compiling vhdl file e:/sum/ieu.vhdl in Library work.
Architecture main of Entity ieu is up to date.
Compiling vhdl file e:/sum/msi.vhdl in Library work.
Architecture main of Entity msi is up to date.
Compiling vhdl file e:/sum/sum.vhdl in Library work.
Entity <sum> (Architecture <Behav>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <sum> (Architecture <Behav>).
INFO:Xst:1304 - Contents of register <pc<15>> in unit <sum> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <pc<14>> in unit <sum> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <pc<13>> in unit <sum> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <pc<12>> in unit <sum> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <pc<11>> in unit <sum> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <pc<10>> in unit <sum> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <pc<9>> in unit <sum> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <pc<8>> in unit <sum> never changes during circuit operation. The register is replaced by logic.
Entity <sum> analyzed. Unit <sum> generated.

Analyzing Entity <clock> (Architecture <main>).
WARNING:Xst:819 - e:/sum/clock.vhdl line 32: The following signals are missing in the process sensitivity list:
   reset.
WARNING:Xst:819 - e:/sum/clock.vhdl line 41: The following signals are missing in the process sensitivity list:
   reset.
Entity <clock> analyzed. Unit <clock> generated.

Analyzing Entity <cu> (Architecture <main>).
INFO:Xst:1561 - e:/sum/cu.vhd line 61: Mux is complete : default of case is discarded
WARNING:Xst:819 - e:/sum/cu.vhd line 39: The following signals are missing in the process sensitivity list:
   reset.
Entity <cu> analyzed. Unit <cu> generated.

Analyzing Entity <ieu> (Architecture <main>).
INFO:Xst:1561 - e:/sum/ieu.vhdl line 32: Mux is complete : default of case is discarded
INFO:Xst:1561 - e:/sum/ieu.vhdl line 46: Mux is complete : default of case is discarded
WARNING:Xst:819 - e:/sum/ieu.vhdl line 50: The following signals are missing in the process sensitivity list:
   cri, crj.
Entity <ieu> analyzed. Unit <ieu> generated.

Analyzing Entity <msi> (Architecture <main>).
Entity <msi> analyzed. Unit <msi> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <msi>.
    Related source file is e:/sum/msi.vhdl.
Unit <msi> synthesized.


Synthesizing Unit <ieu>.
    Related source file is e:/sum/ieu.vhdl.
    Found 1-of-8 decoder for signal <sri>.
    Found 1-of-8 decoder for signal <srj>.
    Summary:
	inferred   2 Decoder(s).
Unit <ieu> synthesized.


Synthesizing Unit <cu>.
    Related source file is e:/sum/cu.vhd.
    Found 32x28-bit ROM for signal <cdata>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0008> created at line 44.
    Found 5-bit register for signal <caddress>.
    Found 1 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   1 ROM(s).
	inferred   5 D-type flip-flop(s).
	inferred   2 Multiplexer(s).
Unit <cu> synthesized.


Synthesizing Unit <clock>.
    Related source file is e:/sum/clock.vhdl.
    Found 1-bit register for signal <mstart>.
    Found 1-bit register for signal <mt0>.
    Found 1-bit register for signal <mt1>.
    Summary:
	inferred   3 D-type flip-flop(s).
Unit <clock> synthesized.


Synthesizing Unit <sum>.
    Related source file is e:/sum/sum.vhdl.
WARNING:Xst:1778 - Inout <sdata> is assigned but never used.
WARNING:Xst:736 - Found 16-bit latch for signal <Mtridata_sdata> created at line 296.
WARNING:Xst:736 - Found 1-bit latch for signal <Mtrien_sdata> created at line 296.
    Found 16-bit tristate buffer for signal <sdata>.
    Found 16-bit adder for signal <$n0001> created at line 220.
    Found 8-bit 16-to-1 multiplexer for signal <$n0014> created at line 111.
    Found 8-bit addsub for signal <$n0032>.
    Found 8-bit register for signal <databus>.
    Found 8-bit register for signal <f1>.
    Found 8-bit register for signal <f2>.
    Found 16-bit register for signal <ir>.
    Found 16-bit register for signal <mar>.
    Found 16-bit register for signal <mdr>.
    Found 16-bit up counter for signal <pc>.
    Found 8-bit register for signal <reg0>.
    Found 8-bit register for signal <reg1>.
    Found 8-bit register for signal <reg2>.
    Found 8-bit register for signal <reg3>.
    Found 8-bit register for signal <reg4>.
    Found 8-bit register for signal <reg5>.
    Found 8-bit register for signal <reg6>.
    Found 8-bit register for signal <reg7>.
    Summary:
	inferred   1 Counter(s).
	inferred 184 D-type flip-flop(s).
	inferred   2 Adder/Subtracter(s).
	inferred   8 Multiplexer(s).
	inferred  16 Tristate(s).
Unit <sum> synthesized.

INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# ROMs                             : 1
 32x28-bit ROM                     : 1
# Adders/Subtractors               : 1
 8-bit addsub                      : 1
# Counters                         : 1
 16-bit up counter                 : 1
# Registers                        : 70
 16-bit register                   : 3
 1-bit register                    : 56
 8-bit register                    : 11
# Latches                          : 2
 1-bit latch                       : 1
 16-bit latch                      : 1
# Multiplexers                     : 3
 8-bit 16-to-1 multiplexer         : 1
 1-bit 2-to-1 multiplexer          : 1
 1-bit 4-to-1 multiplexer          : 1
# Decoders                         : 2
 1-of-8 decoder                    : 2
# Tristates                        : 1
 16-bit tristate buffer            : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:637 - Naming conflict between instance 0 of unit mar and instance mar_0 of unit sum : renaming mar_0 to mar_01.
WARNING:Xst:637 - Naming conflict between instance 1 of unit mar and instance mar_1 of unit sum : renaming mar_1 to mar_16.
WARNING:Xst:637 - Naming conflict between instance 2 of unit mar and instance mar_2 of unit sum : renaming mar_2 to mar_21.
WARNING:Xst:637 - Naming conflict between instance 3 of unit mar and instance mar_3 of unit sum : renaming mar_3 to mar_31.
WARNING:Xst:637 - Naming conflict between instance 4 of unit mar and instance mar_4 of unit sum : renaming mar_4 to mar_41.
WARNING:Xst:637 - Naming conflict between instance 5 of unit mar and instance mar_5 of unit sum : renaming mar_5 to mar_51.
WARNING:Xst:637 - Naming conflict between instance 6 of unit mar and instance mar_6 of unit sum : renaming mar_6 to mar_61.
WARNING:Xst:637 - Naming conflict between instance 7 of unit mar and instance mar_7 of unit sum : renaming mar_7 to mar_71.
WARNING:Xst:637 - Naming conflict between instance 8 of unit mar and instance mar_8 of unit sum : renaming mar_8 to mar_81.
WARNING:Xst:637 - Naming conflict between instance 9 of unit mar and instance mar_9 of unit sum : renaming mar_9 to mar_91.
WARNING:Xst:637 - Naming conflict between instance 10 of unit mar and instance mar_10 of unit sum : renaming mar_10 to mar_101.
WARNING:Xst:637 - Naming conflict between instance 11 of unit mar and instance mar_11 of unit sum : renaming mar_11 to mar_111.
WARNING:Xst:637 - Naming conflict between instance 12 of unit mar and instance mar_12 of unit sum : renaming mar_12 to mar_121.
WARNING:Xst:637 - Naming conflict between instance 13 of unit mar and instance mar_13 of unit sum : renaming mar_13 to mar_131.
WARNING:Xst:637 - Naming conflict between instance 14 of unit mar and instance mar_14 of unit sum : renaming mar_14 to mar_141.
WARNING:Xst:637 - Naming conflict between instance 15 of unit mar and instance mar_15 of unit sum : renaming mar_15 to mar_151.
WARNING:Xst:637 - Naming conflict between instance 15 of unit pc and instance pc_15 of unit sum : renaming pc_15 to pc_151.
WARNING:Xst:637 - Naming conflict between instance 0 of unit pc and instance pc_0 of unit sum : renaming pc_0 to pc_01.
WARNING:Xst:637 - Naming conflict between instance 1 of unit pc and instance pc_1 of unit sum : renaming pc_1 to pc_16.
WARNING:Xst:637 - Naming conflict between instance 2 of unit pc and instance pc_2 of unit sum : renaming pc_2 to pc_21.
WARNING:Xst:637 - Naming conflict between instance 3 of unit pc and instance pc_3 of unit sum : renaming pc_3 to pc_31.
WARNING:Xst:637 - Naming conflict between instance 4 of unit pc and instance pc_4 of unit sum : renaming pc_4 to pc_41.
WARNING:Xst:637 - Naming conflict between instance 5 of unit pc and instance pc_5 of unit sum : renaming pc_5 to pc_51.
WARNING:Xst:637 - Naming conflict between instance 6 of unit pc and instance pc_6 of unit sum : renaming pc_6 to pc_61.
WARNING:Xst:637 - Naming conflict between instance 7 of unit pc and instance pc_7 of unit sum : renaming pc_7 to pc_71.
WARNING:Xst:637 - Naming conflict between instance 8 of unit pc and instance pc_8 of unit sum : renaming pc_8 to pc_81.
WARNING:Xst:637 - Naming conflict between instance 9 of unit pc and instance pc_9 of unit sum : renaming pc_9 to pc_91.
WARNING:Xst:637 - Naming conflict between instance 10 of unit pc and instance pc_10 of unit sum : renaming pc_10 to pc_101.
WARNING:Xst:637 - Naming conflict between instance 11 of unit pc and instance pc_11 of unit sum : renaming pc_11 to pc_111.
WARNING:Xst:637 - Naming conflict between instance 12 of unit pc and instance pc_12 of unit sum : renaming pc_12 to pc_121.
WARNING:Xst:637 - Naming conflict between instance 13 of unit pc and instance pc_13 of unit sum : renaming pc_13 to pc_131.
WARNING:Xst:637 - Naming conflict between instance 14 of unit pc and instance pc_14 of unit sum : renaming pc_14 to pc_141.
WARNING:Xst:528 - Multi-source in Unit <sum> on signal <sdata_4> not replaced by logic
Sources are: I68_11:O, sdata_4:Q
WARNING:Xst:528 - Multi-source in Unit <sum> on signal <sdata_5> not replaced by logic
Sources are: I68_10:O, sdata_5:Q
WARNING:Xst:528 - Multi-source in Unit <sum> on signal <sdata_6> not replaced by logic
Sources are: I68_9:O, sdata_6:Q
WARNING:Xst:528 - Multi-source in Unit <sum> on signal <sdata_7> not replaced by logic
Sources are: I68_8:O, sdata_7:Q
WARNING:Xst:528 - Multi-source in Unit <sum> on signal <sdata_8> not replaced by logic
Sources are: I68_7:O, sdata_8:Q
WARNING:Xst:528 - Multi-source in Unit <sum> on signal <sdata_9> not replaced by logic
Sources are: I68_6:O, sdata_9:Q
WARNING:Xst:528 - Multi-source in Unit <sum> on signal <sdata_10> not replaced by logic
Sources are: I68_5:O, sdata_10:Q
WARNING:Xst:528 - Multi-source in Unit <sum> on signal <sdata_11> not replaced by logic
Sources are: I68_4:O, sdata_11:Q
WARNING:Xst:528 - Multi-source in Unit <sum> on signal <sdata_12> not replaced by logic
Sources are: I68_3:O, sdata_12:Q