pp.vhw

这是一个用VHDL写的简易的CPU的程序

-- D:\SUM
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Wed Nov 21 17:32:45 2007
-- 
-- Notes:
-- 1) This testbench has been automatically generated from
--   your Test Bench Waveform
-- 2) To use this as a user modifiable testbench do the following:
--   - Save it as a file with a .vhd extension (i.e. File->Save As...)
--   - Add it to your project as a testbench source (i.e. Project->Add Source...)
-- 

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY pp IS
END pp;

ARCHITECTURE testbench_arch OF pp IS
-- If you get a compiler error on the following line,
-- from the menu do Options->Configuration select VHDL 87
FILE RESULTS: TEXT OPEN WRITE_MODE IS "results.txt";
	COMPONENT sum
		PORT (
			adress : Out  std_logic_vector (15 DOWNTO 0);
			sdata : InOut  std_logic_vector (15 DOWNTO 0);
			sir : Out  std_logic_vector (15 DOWNTO 0);
			spc : Out  std_logic_vector (15 DOWNTO 0);
			sreg0 : Out  std_logic_vector (7 DOWNTO 0);
			sreg7 : Out  std_logic_vector (7 DOWNTO 0);
			smdrl : Out  std_logic_vector (7 DOWNTO 0);
			lig : Out  std_logic_vector (1 DOWNTO 0);
			clkg : In  std_logic;
			ncs : Out  std_logic;
			nwr : Out  std_logic;
			nrd : Out  std_logic;
			nbl : Out  std_logic;
			nbh : Out  std_logic;
			reset : In  std_logic
		);
	END COMPONENT;

	SIGNAL adress : std_logic_vector (15 DOWNTO 0);
	SIGNAL sdata : std_logic_vector (15 DOWNTO 0);
	SIGNAL sir : std_logic_vector (15 DOWNTO 0);
	SIGNAL spc : std_logic_vector (15 DOWNTO 0);
	SIGNAL sreg0 : std_logic_vector (7 DOWNTO 0);
	SIGNAL sreg7 : std_logic_vector (7 DOWNTO 0);
	SIGNAL smdrl : std_logic_vector (7 DOWNTO 0);
	SIGNAL lig : std_logic_vector (1 DOWNTO 0);
	SIGNAL clkg : std_logic;
	SIGNAL ncs : std_logic;
	SIGNAL nwr : std_logic;
	SIGNAL nrd : std_logic;
	SIGNAL nbl : std_logic;
	SIGNAL nbh : std_logic;
	SIGNAL reset : std_logic;

BEGIN
	UUT : sum
	PORT MAP (
		adress => adress,
		sdata => sdata,
		sir => sir,
		spc => spc,
		sreg0 => sreg0,
		sreg7 => sreg7,
		smdrl => smdrl,
		lig => lig,
		clkg => clkg,
		ncs => ncs,
		nwr => nwr,
		nrd => nrd,
		nbl => nbl,
		nbh => nbh,
		reset => reset
	);

	PROCESS -- clock process for clkg,
	BEGIN
		CLOCK_LOOP : LOOP
		clkg <= transport '0';
		WAIT FOR 10 ns;
		clkg <= transport '1';
		WAIT FOR 10 ns;
		WAIT FOR 40 ns;
		clkg <= transport '0';
		WAIT FOR 40 ns;
		END LOOP CLOCK_LOOP;
	END PROCESS;

	PROCESS   -- Process for clkg
		VARIABLE TX_OUT : LINE;
		VARIABLE TX_ERROR : INTEGER := 0;

		PROCEDURE CHECK_adress(
			next_adress : std_logic_vector (15 DOWNTO 0);
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (adress /= next_adress) THEN 
				STD.TEXTIO.write(TX_LOC,string'("Error at time="));
				STD.TEXTIO.write(TX_LOC, TX_TIME);
				STD.TEXTIO.write(TX_LOC,string'("ns adress="));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, adress);
				STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_adress);
				STD.TEXTIO.write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				STD.TEXTIO.writeline(results, TX_LOC);
				STD.TEXTIO.Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		PROCEDURE CHECK_sir(
			next_sir : std_logic_vector (15 DOWNTO 0);
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (sir /= next_sir) THEN 
				STD.TEXTIO.write(TX_LOC,string'("Error at time="));
				STD.TEXTIO.write(TX_LOC, TX_TIME);
				STD.TEXTIO.write(TX_LOC,string'("ns sir="));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, sir);
				STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_sir);
				STD.TEXTIO.write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				STD.TEXTIO.writeline(results, TX_LOC);
				STD.TEXTIO.Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		PROCEDURE CHECK_spc(
			next_spc : std_logic_vector (15 DOWNTO 0);
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (spc /= next_spc) THEN 
				STD.TEXTIO.write(TX_LOC,string'("Error at time="));
				STD.TEXTIO.write(TX_LOC, TX_TIME);
				STD.TEXTIO.write(TX_LOC,string'("ns spc="));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, spc);
				STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_spc);
				STD.TEXTIO.write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				STD.TEXTIO.writeline(results, TX_LOC);
				STD.TEXTIO.Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		PROCEDURE CHECK_sreg0(
			next_sreg0 : std_logic_vector (7 DOWNTO 0);
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (sreg0 /= next_sreg0) THEN 
				STD.TEXTIO.write(TX_LOC,string'("Error at time="));
				STD.TEXTIO.write(TX_LOC, TX_TIME);
				STD.TEXTIO.write(TX_LOC,string'("ns sreg0="));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, sreg0);
				STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_sreg0);
				STD.TEXTIO.write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				STD.TEXTIO.writeline(results, TX_LOC);
				STD.TEXTIO.Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		PROCEDURE CHECK_sreg7(
			next_sreg7 : std_logic_vector (7 DOWNTO 0);
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (sreg7 /= next_sreg7) THEN 
				STD.TEXTIO.write(TX_LOC,string'("Error at time="));
				STD.TEXTIO.write(TX_LOC, TX_TIME);
				STD.TEXTIO.write(TX_LOC,string'("ns sreg7="));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, sreg7);
				STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_sreg7);
				STD.TEXTIO.write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				STD.TEXTIO.writeline(results, TX_LOC);
				STD.TEXTIO.Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		PROCEDURE CHECK_smdrl(
			next_smdrl : std_logic_vector (7 DOWNTO 0);
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (smdrl /= next_smdrl) THEN