sum.twr

这是一个用VHDL写的简易的CPU的程序

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Release 6.2i Trace G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.

C:/Xilinx/bin/nt/trce.exe -intstyle ise -e 3 -l 3 -xml sum sum.ncd -o sum.twr
sum.pcf


Design file:              sum.ncd
Physical constraint file: sum.pcf
Device,speed:             xcv200,-4 (FINAL 1.123 2003-12-13)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
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INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Clock clkg to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
lig<0>      |   15.521(R)|clk               |   0.000|
lig<1>      |   14.881(F)|clk               |   0.000|
nbh         |   16.323(R)|clk               |   0.000|
nbl         |   16.632(R)|clk               |   0.000|
ncs         |   16.611(R)|clk               |   0.000|
nrd         |   16.328(R)|clk               |   0.000|
nwr         |   17.077(R)|clk               |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock clkg
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clkg           |    4.675|         |         |    4.484|
---------------+---------+---------+---------+---------+

Analysis completed Fri Nov 23 13:45:10 2007
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Peak Memory Usage: 52 MB