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来自「这是一个用VHDL写的简易的CPU的程序」· 代码 · 共 44 行

# Reading C:/Modeltech_xe/tcl/vsim/pref.tcl 
# do ss.fdo 
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim XE vcom 5.6a Compiler 2002.04 Apr 29 2002
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity clock
# -- Compiling architecture main of clock
# Model Technology ModelSim XE vcom 5.6a Compiler 2002.04 Apr 29 2002
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package textio
# -- Loading package std_logic_textio
# -- Compiling entity ss
# -- Compiling architecture testbench_arch of ss
# -- Loading entity clock
# -- Compiling configuration clock_cfg
# -- Loading entity ss
# -- Loading architecture testbench_arch of ss
# vsim -lib work -t 1ps ss 
# Loading C:/Modeltech_xe/win32xoem/../std.standard
# Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body)
# Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body)
# Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body)
# Loading C:/Modeltech_xe/win32xoem/../std.textio(body)
# Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body)
# Loading work.ss(testbench_arch)
# Loading work.clock(main)
# .wave
# .structure
# .signals
# ** Failure: Simulation successful (not a failure).  No problems detected. 
#    Time: 960 ns  Iteration: 0  Instance: /ss
# Break at ss.vhw line 132
# Simulation Breakpoint: Break at ss.vhw line 132
# MACRO ./ss.fdo PAUSED at line 13
destroy .wave
destroy .signals
destroy .structure