cu.vhd

这是一个用VHDL写的简易的CPU的程序

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    21:58:01 10/29/2007 
-- Design Name: 
-- Module Name:    cu - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity cu is
    Port ( t1 : in  STD_LOGIC;
           databus : in  STD_LOGIC_VECTOR (7 downto 0);
           op : in  STD_LOGIC_VECTOR (4 downto 0);
           reset : in  STD_LOGIC;
           control : out  STD_LOGIC_VECTOR (22 downto 0));
end cu;
architecture main of cu is
signal cdata :std_logic_vector(27 downto 0);
signal caddress:std_logic_vector(4 downto 0);
begin
	process(t1)
	begin
	if reset='1' then
		caddress(4 downto 0)<="00000";
	elsif t1='1' and t1'event then
		case cdata(6 downto 5) is
		when "00" =>
			caddress(4 downto 0)<=cdata(4 downto 0);
		when "10" =>
			if databus(7 downto 0)="00000000" then
				caddress(1 downto 0)<=cdata(1 downto 0);
				caddress(3 downto 2)<="11";
				caddress(4)<=cdata(4);
			else
				caddress(4 downto 0)<=cdata(4 downto 0);
			end if;
		when "01" =>
			caddress(3 downto 1)<=op(4 downto 2);
			caddress(4)<='0';
			caddress(0)<='0';
		when "11" =>
			caddress(2 downto 0)<=cdata(2 downto 0);
			caddress(4 downto 3)<=op(1 downto 0);
		when others=>
			caddress(4 downto 0)<="00000";
		end case;	
	end if;
	end process;
	
	process(caddress)
	begin
		case caddress(4 downto 0) is
		when "00000"=>cdata(27 downto 0)<="0000000001000100000000000001";
		when "00001"=>cdata(27 downto 0)<="0000000000100000101110100000";
		when "00010"=>cdata(27 downto 0)<="0010100000000000000000000000";
		when "00100"=>cdata(27 downto 0)<="1001000000000000000000000000";
		when "00110"=>cdata(27 downto 0)<="0110010000000000000000000101";
		when "00101"=>cdata(27 downto 0)<="1000001000000000000001100111";
		when "00111"=>cdata(27 downto 0)<="0010000100000000000000001001";
		when "01001"=>cdata(27 downto 0)<="0000000000000000110110000000";
		when "01111"=>cdata(27 downto 0)<="0000000000000000101110010000";
		when "10000"=>cdata(27 downto 0)<="1011000000000000000000000000";
		when "01010"=>cdata(27 downto 0)<="0010000000010000000000001011";
		when "01011"=>cdata(27 downto 0)<="0100000000001000000000000011";
		when "00011"=>cdata(27 downto 0)<="1111000000000000000000000000";
		when "01110"=>cdata(27 downto 0)<="0010000000000000000001000000";
		when "01100"=>cdata(27 downto 0)<="0110000000000010000000001101";
		when "01101"=>cdata(27 downto 0)<="1000000000000001000000000000";
		when others =>cdata(27 downto 0)<="0000000000000000000000000000";
		end case;
	end process;
	control(22 downto 2)<=cdata(27 downto 7);
	control(1 downto 0)<=op(1 downto 0);
end main;