sum.par

这是一个用VHDL写的简易的CPU的程序

Release 6.2i Par G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.

hit58::  Fri Nov 23 13:45:06 2007


C:/Xilinx/bin/nt/par.exe -w -intstyle ise -ol std -t 1 sum_map.ncd sum.ncd
sum.pcf 


Constraints file: sum.pcf

Loading device database for application Par from file "sum_map.ncd".
   "sum" is an NCD, version 2.38, device xcv200, package pq240, speed -4
Loading device for application Par from file 'v200.nph' in environment
C:/Xilinx.
Device speed data version:  FINAL 1.123 2003-12-13.


Resolved that IOB <sdata<0>> must be placed at site P160.
Resolved that IOB <sdata<1>> must be placed at site P161.
Resolved that IOB <sdata<2>> must be placed at site P162.
Resolved that IOB <sdata<3>> must be placed at site P163.
Resolved that IOB <sdata<4>> must be placed at site P167.
Resolved that IOB <sdata<5>> must be placed at site P168.
Resolved that IOB <sdata<6>> must be placed at site P169.
Resolved that IOB <sdata<7>> must be placed at site P170.
Resolved that IOB <sdata<8>> must be placed at site P202.
Resolved that IOB <sdata<9>> must be placed at site P201.
Resolved that IOB <sdata<10>> must be placed at site P200.
Resolved that IOB <sdata<11>> must be placed at site P199.
Resolved that IOB <sdata<12>> must be placed at site P195.
Resolved that IOB <sdata<13>> must be placed at site P194.
Resolved that IOB <sdata<14>> must be placed at site P193.
Resolved that IOB <sdata<15>> must be placed at site P192.
Resolved that IOB <spc<10>> must be placed at site P67.
Resolved that IOB <spc<11>> must be placed at site P57.
Resolved that IOB <spc<12>> must be placed at site P52.
Resolved that IOB <spc<13>> must be placed at site P46.
Resolved that IOB <spc<14>> must be placed at site P42.
Resolved that IOB <spc<15>> must be placed at site P31.
Resolved that IOB <sir<10>> must be placed at site P5.
Resolved that IOB <sir<11>> must be placed at site P4.
Resolved that IOB <sir<12>> must be placed at site P3.
Resolved that IOB <sir<13>> must be placed at site P238.
Resolved that IOB <sir<14>> must be placed at site P237.
Resolved that IOB <sir<15>> must be placed at site P236.
Resolved that IOB <lig<0>> must be placed at site P110.
Resolved that IOB <lig<1>> must be placed at site P111.
Resolved that IOB <reset> must be placed at site P33.
Resolved that IOB <sreg0<0>> must be placed at site P19.
Resolved that IOB <sreg0<1>> must be placed at site P18.
Resolved that IOB <sreg0<2>> must be placed at site P17.
Resolved that IOB <sreg0<3>> must be placed at site P13.
Resolved that IOB <sreg0<4>> must be placed at site P12.
Resolved that IOB <sreg0<5>> must be placed at site P11.
Resolved that IOB <sreg0<6>> must be placed at site P10.
Resolved that IOB <sreg0<7>> must be placed at site P9.
Resolved that IOB <sreg7<0>> must be placed at site P223.
Resolved that IOB <sreg7<1>> must be placed at site P222.
Resolved that IOB <sreg7<2>> must be placed at site P221.
Resolved that IOB <sreg7<3>> must be placed at site P220.
Resolved that IOB <sreg7<4>> must be placed at site P218.
Resolved that IOB <sreg7<5>> must be placed at site P217.
Resolved that IOB <sreg7<6>> must be placed at site P216.
Resolved that IOB <sreg7<7>> must be placed at site P215.
Resolved that GCLKIOB <clkg> must be placed at site P92.
Resolved that IOB <spc<0>> must be placed at site P28.
Resolved that IOB <spc<1>> must be placed at site P27.
Resolved that IOB <spc<2>> must be placed at site P26.
Resolved that IOB <spc<3>> must be placed at site P25.
Resolved that IOB <sir<0>> must be placed at site P235.
Resolved that IOB <spc<4>> must be placed at site P24.
Resolved that IOB <sir<1>> must be placed at site P234.
Resolved that IOB <spc<5>> must be placed at site P23.
Resolved that IOB <spc<6>> must be placed at site P21.
Resolved that IOB <sir<2>> must be placed at site P232.
Resolved that IOB <spc<7>> must be placed at site P20.
Resolved that IOB <sir<3>> must be placed at site P231.
Resolved that IOB <sir<4>> must be placed at site P230.
Resolved that IOB <spc<8>> must be placed at site P74.
Resolved that IOB <sir<5>> must be placed at site P229.
Resolved that IOB <spc<9>> must be placed at site P68.
Resolved that IOB <sir<6>> must be placed at site P228.
Resolved that IOB <sir<7>> must be placed at site P224.
Resolved that IOB <sir<8>> must be placed at site P7.
Resolved that IOB <sir<9>> must be placed at site P6.
Resolved that IOB <smdrl<0>> must be placed at site P125.
Resolved that IOB <nbh> must be placed at site P189.
Resolved that IOB <smdrl<1>> must be placed at site P124.
Resolved that IOB <smdrl<2>> must be placed at site P109.
Resolved that IOB <nbl> must be placed at site P191.
Resolved that IOB <smdrl<3>> must be placed at site P108.
Resolved that IOB <smdrl<4>> must be placed at site P107.
Resolved that IOB <smdrl<5>> must be placed at site P99.
Resolved that IOB <smdrl<6>> must be placed at site P93.
Resolved that IOB <ncs> must be placed at site P159.
Resolved that IOB <smdrl<7>> must be placed at site P78.
Resolved that IOB <adress<10>> must be placed at site P185.
Resolved that IOB <adress<11>> must be placed at site P208.
Resolved that IOB <nrd> must be placed at site P188.
Resolved that IOB <adress<12>> must be placed at site P207.
Resolved that IOB <adress<13>> must be placed at site P206.
Resolved that IOB <adress<14>> must be placed at site P205.
Resolved that IOB <adress<15>> must be placed at site P187.
Resolved that IOB <nwr> must be placed at site P171.
Resolved that IOB <adress<0>> must be placed at site P153.
Resolved that IOB <adress<1>> must be placed at site P154.
Resolved that IOB <adress<2>> must be placed at site P155.
Resolved that IOB <adress<3>> must be placed at site P156.
Resolved that IOB <adress<4>> must be placed at site P157.
Resolved that IOB <adress<5>> must be placed at site P173.
Resolved that IOB <adress<6>> must be placed at site P174.
Resolved that IOB <adress<7>> must be placed at site P175.
Resolved that IOB <adress<8>> must be placed at site P176.
Resolved that IOB <adress<9>> must be placed at site P186.


Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs            96 out of 166    57%
      Number of LOCed External IOBs   96 out of 96    100%

   Number of SLICEs                  230 out of 2352    9%

   Number of GCLKs                     1 out of 4      25%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:989f00) REAL time: 0 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
....
Phase 5.8 (Checksum:a58ffb) REAL time: 0 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 0 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs 

Writing design to file sum.ncd.

Total REAL time to Placer completion: 0 secs 
Total CPU time to Placer completion: 1 secs 


Phase 1: 1803 unrouted;       REAL time: 0 secs 

Phase 2: 1713 unrouted;       REAL time: 0 secs 

Phase 3: 536 unrouted;       REAL time: 2 secs 

Phase 4: 0 unrouted;       REAL time: 2 secs 

Total REAL time to Router completion: 2 secs 
Total CPU time to Router completion: 2 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|               clk          |  Global  |    3   |  0.010     |  0.570      |
+----------------------------+----------+--------+------------+-------------+
|            u1_mt0          |   Local  |   91   |  2.746     |  6.645      |
+----------------------------+----------+--------+------------+-------------+
|            u1_mt1          |   Local  |   40   |  3.242     |  6.271      |
+----------------------------+----------+--------+------------+-------------+
|          u1_mt0_1          |   Local  |   58   |  2.427     |  5.376      |
+----------------------------+----------+--------+------------+-------------+


   The Delay Summary Report

   The SCORE FOR THIS DESIGN is: 393


The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

   The AVERAGE CONNECTION DELAY for this design is:        2.759
   The MAXIMUM PIN DELAY IS:                               7.954
   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   5.872

   Listing Pin Delays by value: (nsec)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 8.00  d >= 8.00
   ---------   ---------   ---------   ---------   ---------   ---------
         179         400         513         348         363           0

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 3 secs 
Total CPU time to PAR completion: 2 secs 

Peak Memory Usage:  57 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file sum.ncd.


PAR done.