clock.vhdl

来自「这是一个用VHDL写的简易的CPU的程序」· VHDL 代码 · 共 53 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity clock is
    Port ( clk : in std_logic;
           reset : in std_logic;
           t0 : out std_logic;
           t1 : out std_logic);
end clock;

architecture main of clock is
	signal mstart:std_logic:='0';
	signal mt0:std_logic:='0';
	signal mt1:std_logic:='0';
begin
	process(clk,reset)
	begin
		if reset='1'then 
			mt0<='0';
		elsif clk='1' and clk'event then
			mt0<=not mt0;
		end if;
	end process;

	process(clk,mstart,reset)
	begin
		if reset='1' then
			mt1<='0';
		elsif mstart='1' and clk='0' and clk'event then
			mt1<= not mt1;
		end if;				
	end process;

	process(mt0,reset)
	begin
		if reset='1' then
			mstart<='0';
		elsif mt0='0' and mt0'event then
			mstart<='1';
		end if;
	end process;

	t0<=mt0;
	t1<=mt1;
end main;