📄 sum.mrp
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| adress<8> | IOB | OUTPUT | LVTTL | 12 | SLOW | OUTFF | | || adress<9> | IOB | OUTPUT | LVTTL | 12 | SLOW | OUTFF | | || adress<10> | IOB | OUTPUT | LVTTL | 12 | SLOW | OUTFF | | || adress<11> | IOB | OUTPUT | LVTTL | 12 | SLOW | OUTFF | | || adress<12> | IOB | OUTPUT | LVTTL | 12 | SLOW | OUTFF | | || adress<13> | IOB | OUTPUT | LVTTL | 12 | SLOW | OUTFF | | || adress<14> | IOB | OUTPUT | LVTTL | 12 | SLOW | OUTFF | | || adress<15> | IOB | OUTPUT | LVTTL | 12 | SLOW | OUTFF | | || lig<0> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || lig<1> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || nbh | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || nbl | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || ncs | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || nrd | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || nwr | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || reset | IOB | INPUT | LVTTL | | | | | || sdata<0> | IOB | BIDIR | LVTTL | 12 | SLOW | | | || sdata<1> | IOB | BIDIR | LVTTL | 12 | SLOW | | | || sdata<2> | IOB | BIDIR | LVTTL | 12 | SLOW | | | || sdata<3> | IOB | BIDIR | LVTTL | 12 | SLOW | | | || sdata<4> | IOB | BIDIR | LVTTL | 12 | SLOW | | | || sdata<5> | IOB | BIDIR | LVTTL | 12 | SLOW | | | || sdata<6> | IOB | BIDIR | LVTTL | 12 | SLOW | | | || sdata<7> | IOB | BIDIR | LVTTL | 12 | SLOW | | | || sdata<8> | IOB | BIDIR | LVTTL | 12 | SLOW | | | || sdata<9> | IOB | BIDIR | LVTTL | 12 | SLOW | | | || sdata<10> | IOB | BIDIR | LVTTL | 12 | SLOW | | | || sdata<11> | IOB | BIDIR | LVTTL | 12 | SLOW | | | || sdata<12> | IOB | BIDIR | LVTTL | 12 | SLOW | | | || sdata<13> | IOB | BIDIR | LVTTL | 12 | SLOW | | | || sdata<14> | IOB | BIDIR | LVTTL | 12 | SLOW | | | || sdata<15> | IOB | BIDIR | LVTTL | 12 | SLOW | | | || sir<0> | IOB | OUTPUT | LVTTL | 12 | SLOW | OUTFF | | || sir<1> | IOB | OUTPUT | LVTTL | 12 | SLOW | OUTFF | | || sir<2> | IOB | OUTPUT | LVTTL | 12 | SLOW | OUTFF | | || sir<3> | IOB | OUTPUT | LVTTL | 12 | SLOW | OUTFF | | || sir<4> | IOB | OUTPUT | LVTTL | 12 | SLOW | OUTFF | | || sir<5> | IOB | OUTPUT | LVTTL | 12 | SLOW | OUTFF | | || sir<6> | IOB | OUTPUT | LVTTL | 12 | SLOW | OUTFF | | || sir<7> | IOB | OUTPUT | LVTTL | 12 | SLOW | OUTFF | | || sir<8> | IOB | OUTPUT | LVTTL | 12 | SLOW | OUTFF | | || sir<9> | IOB | OUTPUT | LVTTL | 12 | SLOW | OUTFF | | || sir<10> | IOB | OUTPUT | LVTTL | 12 | SLOW | OUTFF | | || sir<11> | IOB | OUTPUT | LVTTL | 12 | SLOW | OUTFF | | || sir<12> | IOB | OUTPUT | LVTTL | 12 | SLOW | OUTFF | | || sir<13> | IOB | OUTPUT | LVTTL | 12 | SLOW | OUTFF | | || sir<14> | IOB | OUTPUT | LVTTL | 12 | SLOW | OUTFF | | || sir<15> | IOB | OUTPUT | LVTTL | 12 | SLOW | OUTFF | | || smdrl<0> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || smdrl<1> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || smdrl<2> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || smdrl<3> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || smdrl<4> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || smdrl<5> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || smdrl<6> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || smdrl<7> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || spc<0> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || spc<1> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || spc<2> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || spc<3> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || spc<4> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || spc<5> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || spc<6> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || spc<7> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || spc<8> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || spc<9> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || spc<10> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || spc<11> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || spc<12> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || spc<13> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || spc<14> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || spc<15> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || sreg0<0> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || sreg0<1> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || sreg0<2> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || sreg0<3> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || sreg0<4> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || sreg0<5> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || sreg0<6> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || sreg0<7> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || sreg7<0> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || sreg7<1> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || sreg7<2> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || sreg7<3> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || sreg7<4> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || sreg7<5> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || sreg7<6> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || sreg7<7> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |+------------------------------------------------------------------------------------------------------------------------+Section 7 - RPMs----------------Section 8 - Guide Report------------------------Guide not run on this design.Section 9 - Area Group Summary------------------------------No area groups were found in this design.Section 10 - Modular Design Summary-----------------------------------Modular Design not used for this design.Section 11 - Timing Report--------------------------This design was not run using timing mode.Section 12 - Configuration String Details-----------------------------------------Use the "-detail" map option to print out Configuration StringsSection 13 - Additional Device Resource Counts----------------------------------------------Number of JTAG Gates for IOBs = 97Number of Equivalent Gates for Design = 4,016Number of RPM Macros = 0Number of Hard Macros = 0PCI IOBs = 0PCI LOGICs = 0CAPTUREs = 0BSCANs = 0STARTUPs = 0DLLs = 0GCLKIOBs = 1GCLKs = 1Block RAMs = 0TBUFs = 0Total Registers (Flops & Latches in Slices & IOBs) not driven by LUTs = 159IOB Latches not driven by LUTs = 0IOB Latches = 0IOB Flip Flops not driven by LUTs = 16IOB Flip Flops = 32Unbonded IOBs = 0Bonded IOBs = 96Shift Registers = 0Static Shift Registers = 0Dynamic Shift Registers = 016x1 ROMs = 016x1 RAMs = 032x1 RAMs = 0Dual Port RAMs = 0MULTANDs = 0MUXF5s + MUXF6s = 594 input LUTs used as Route-Thrus = 154 input LUTs = 312Slice Latches not driven by LUTs = 0Slice Latches = 0Slice Flip Flops not driven by LUTs = 143Slice Flip Flops = 185Slices = 230Number of LUT signals with 4 loads = 3Number of LUT signals with 3 loads = 2Number of LUT signals with 2 loads = 32Number of LUT signals with 1 load = 236NGM Average fanout of LUT = 2.88NGM Maximum fanout of LUT = 35NGM Average fanin for LUT = 3.6378Number of LUT symbols = 312Number of IPAD symbols = 2Number of IBUF symbols = 17Number of BIPAD symbols = 16⌨️ 快捷键说明
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