sum.mrp

这是一个用VHDL写的简易的CPU的程序

Release 6.2i Map G.28
Xilinx Mapping Report File for Design 'sum'

Design Information
------------------
Command Line   : C:/Xilinx/bin/nt/map.exe -intstyle ise -p xcv200-pq240-4 -cm
area -pr b -k 4 -c 100 -tx off -o sum_map.ncd sum.ngd sum.pcf 
Target Device  : xv200
Target Package : pq240
Target Speed   : -4
Mapper Version : virtex -- $Revision: 1.16.8.1 $
Mapped Date    : Fri Nov 23 13:45:04 2007

Design Summary
--------------
Number of errors:      0
Number of warnings:   16
Logic Utilization:
  Number of Slice Flip Flops:       185 out of  4,704    3%
  Number of 4 input LUTs:           312 out of  4,704    6%
Logic Distribution:
    Number of occupied Slices:                         230 out of  2,352    9%
    Number of Slices containing only related logic:    230 out of    230  100%
    Number of Slices containing unrelated logic:         0 out of    230    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          327 out of  4,704    6%
      Number used as logic:                       312
      Number used as a route-thru:                 15
   Number of bonded IOBs:            96 out of    166   57%
      IOB Flip Flops:                              32
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%

Total equivalent gate count for design:  4,016
Additional JTAG gate count for IOBs:  4,656
Peak Memory Usage:  66 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group Summary
Section 10 - Modular Design Summary
Section 11 - Timing Report
Section 12 - Configuration String Information
Section 13 - Additional Device Resource Counts

Section 1 - Errors
------------------

Section 2 - Warnings
--------------------
WARNING:Pack:1402 - The register Mtrien_sdata_13 has the property IOB=TRUE, but
   was not packed into the output side of an I/O component. The register has
   both set and reset signal connections.
WARNING:Pack:1402 - The register Mtrien_sdata_14 has the property IOB=TRUE, but
   was not packed into the output side of an I/O component. The register has
   both set and reset signal connections.
WARNING:Pack:1402 - The register Mtrien_sdata_15 has the property IOB=TRUE, but
   was not packed into the output side of an I/O component. The register has
   both set and reset signal connections.
WARNING:Pack:1402 - The register Mtrien_sdata has the property IOB=TRUE, but was
   not packed into the output side of an I/O component. The register has both
   set and reset signal connections.
WARNING:Pack:1402 - The register Mtrien_sdata_1 has the property IOB=TRUE, but
   was not packed into the output side of an I/O component. The register has
   both set and reset signal connections.
WARNING:Pack:1402 - The register Mtrien_sdata_2 has the property IOB=TRUE, but
   was not packed into the output side of an I/O component. The register has
   both set and reset signal connections.
WARNING:Pack:1402 - The register Mtrien_sdata_3 has the property IOB=TRUE, but
   was not packed into the output side of an I/O component. The register has
   both set and reset signal connections.
WARNING:Pack:1402 - The register Mtrien_sdata_4 has the property IOB=TRUE, but
   was not packed into the output side of an I/O component. The register has
   both set and reset signal connections.
WARNING:Pack:1402 - The register Mtrien_sdata_5 has the property IOB=TRUE, but
   was not packed into the output side of an I/O component. The register has
   both set and reset signal connections.
WARNING:Pack:1402 - The register Mtrien_sdata_6 has the property IOB=TRUE, but
   was not packed into the output side of an I/O component. The register has
   both set and reset signal connections.
WARNING:Pack:1402 - The register Mtrien_sdata_7 has the property IOB=TRUE, but
   was not packed into the output side of an I/O component. The register has
   both set and reset signal connections.
WARNING:Pack:1402 - The register Mtrien_sdata_8 has the property IOB=TRUE, but
   was not packed into the output side of an I/O component. The register has
   both set and reset signal connections.
WARNING:Pack:1402 - The register Mtrien_sdata_9 has the property IOB=TRUE, but
   was not packed into the output side of an I/O component. The register has
   both set and reset signal connections.
WARNING:Pack:1402 - The register Mtrien_sdata_10 has the property IOB=TRUE, but
   was not packed into the output side of an I/O component. The register has
   both set and reset signal connections.
WARNING:Pack:1402 - The register Mtrien_sdata_11 has the property IOB=TRUE, but
   was not packed into the output side of an I/O component. The register has
   both set and reset signal connections.
WARNING:Pack:1402 - The register Mtrien_sdata_12 has the property IOB=TRUE, but
   was not packed into the output side of an I/O component. The register has
   both set and reset signal connections.

Section 3 - Informational
-------------------------
INFO:LIT:95 - All of the external outputs in this design are using slew rate
   limited output drivers. The delay on speed critical outputs can be
   dramatically reduced by designating them as fast outputs in the schematic.
INFO:MapLib:562 - No environment variables are currently set.

Section 4 - Removed Logic Summary
---------------------------------
   2 block(s) optimized away

Section 5 - Removed Logic
-------------------------

Optimized Block(s):
TYPE 		BLOCK
GND 		XST_GND
VCC 		XST_VCC

To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.

Section 6 - IOB Properties
--------------------------

+------------------------------------------------------------------------------------------------------------------------+
| IOB Name                           | Type    | Direction | IO Standard | Drive    | Slew | Reg (s)  | Resistor | IOB   |
|                                    |         |           |             | Strength | Rate |          |          | Delay |
+------------------------------------------------------------------------------------------------------------------------+
| clkg                               | GCLKIOB | INPUT     | LVTTL       |          |      |          |          |       |
| adress<0>                          | IOB     | OUTPUT    | LVTTL       | 12       | SLOW | OUTFF    |          |       |
| adress<1>                          | IOB     | OUTPUT    | LVTTL       | 12       | SLOW | OUTFF    |          |       |
| adress<2>                          | IOB     | OUTPUT    | LVTTL       | 12       | SLOW | OUTFF    |          |       |
| adress<3>                          | IOB     | OUTPUT    | LVTTL       | 12       | SLOW | OUTFF    |          |       |
| adress<4>                          | IOB     | OUTPUT    | LVTTL       | 12       | SLOW | OUTFF    |          |       |
| adress<5>                          | IOB     | OUTPUT    | LVTTL       | 12       | SLOW | OUTFF    |          |       |
| adress<6>                          | IOB     | OUTPUT    | LVTTL       | 12       | SLOW | OUTFF    |          |       |
| adress<7>                          | IOB     | OUTPUT    | LVTTL       | 12       | SLOW | OUTFF    |          |       |