pp.ant

这是一个用VHDL写的简易的CPU的程序

-- D:\SUM
-- VHDL Annotation Test Bench created by
-- HDL Bencher 6.1i
-- Wed Nov 21 17:32:45 2007

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY pp IS
END pp;

ARCHITECTURE testbench_arch OF pp IS
-- If you get a compiler error on the following line,
-- from the menu do Options->Configuration select VHDL 87
FILE RESULTS: TEXT OPEN WRITE_MODE IS "d:\sum\pp.ano";
	COMPONENT sum
		PORT (
			adress : Out  std_logic_vector (15 DOWNTO 0);
			sdata : InOut  std_logic_vector (15 DOWNTO 0);
			sir : Out  std_logic_vector (15 DOWNTO 0);
			spc : Out  std_logic_vector (15 DOWNTO 0);
			sreg0 : Out  std_logic_vector (7 DOWNTO 0);
			sreg7 : Out  std_logic_vector (7 DOWNTO 0);
			smdrl : Out  std_logic_vector (7 DOWNTO 0);
			lig : Out  std_logic_vector (1 DOWNTO 0);
			clkg : In  std_logic;
			ncs : Out  std_logic;
			nwr : Out  std_logic;
			nrd : Out  std_logic;
			nbl : Out  std_logic;
			nbh : Out  std_logic;
			reset : In  std_logic
		);
	END COMPONENT;

	SIGNAL adress : std_logic_vector (15 DOWNTO 0);
	SIGNAL sdata : std_logic_vector (15 DOWNTO 0);
	SIGNAL sir : std_logic_vector (15 DOWNTO 0);
	SIGNAL spc : std_logic_vector (15 DOWNTO 0);
	SIGNAL sreg0 : std_logic_vector (7 DOWNTO 0);
	SIGNAL sreg7 : std_logic_vector (7 DOWNTO 0);
	SIGNAL smdrl : std_logic_vector (7 DOWNTO 0);
	SIGNAL lig : std_logic_vector (1 DOWNTO 0);
	SIGNAL clkg : std_logic;
	SIGNAL ncs : std_logic;
	SIGNAL nwr : std_logic;
	SIGNAL nrd : std_logic;
	SIGNAL nbl : std_logic;
	SIGNAL nbh : std_logic;
	SIGNAL reset : std_logic;

BEGIN
	UUT : sum
	PORT MAP (
		adress => adress,
		sdata => sdata,
		sir => sir,
		spc => spc,
		sreg0 => sreg0,
		sreg7 => sreg7,
		smdrl => smdrl,
		lig => lig,
		clkg => clkg,
		ncs => ncs,
		nwr => nwr,
		nrd => nrd,
		nbl => nbl,
		nbh => nbh,
		reset => reset
	);

	PROCESS -- clock process for clkg,
		VARIABLE TX_TIME : INTEGER :=0;

		PROCEDURE ANNOTATE_adress(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",adress,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, adress);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_sir(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",sir,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, sir);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_spc(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",spc,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, spc);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_sreg0(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",sreg0,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, sreg0);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_sreg7(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",sreg7,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, sreg7);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_smdrl(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",smdrl,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, smdrl);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_lig(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",lig,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, lig);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_ncs(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",ncs,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, ncs);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_nwr(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",nwr,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, nwr);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_nrd(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",nrd,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, nrd);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_nbl(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",nbl,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, nbl);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_nbh(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",nbh,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, nbh);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_sdata(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",sdata,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, sdata);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

	BEGIN
		CLOCK_LOOP : LOOP
		clkg <= transport '0';
		WAIT FOR 10 ns;
		TX_TIME := TX_TIME + 10;
		clkg <= transport '1';
		WAIT FOR 10 ns;
		TX_TIME := TX_TIME + 10;
		ANNOTATE_adress(TX_TIME);
		ANNOTATE_sir(TX_TIME);
		ANNOTATE_spc(TX_TIME);
		ANNOTATE_sreg0(TX_TIME);
		ANNOTATE_sreg7(TX_TIME);
		ANNOTATE_smdrl(TX_TIME);
		ANNOTATE_lig(TX_TIME);
		ANNOTATE_ncs(TX_TIME);
		ANNOTATE_nwr(TX_TIME);
		ANNOTATE_nrd(TX_TIME);
		ANNOTATE_nbl(TX_TIME);
		ANNOTATE_nbh(TX_TIME);
		ANNOTATE_sdata(TX_TIME);
		WAIT FOR 40 ns;
		TX_TIME := TX_TIME + 40;
		clkg <= transport '0';
		WAIT FOR 40 ns;
		TX_TIME := TX_TIME + 40;
		END LOOP CLOCK_LOOP;
	END PROCESS;

	PROCESS   -- Process for clkg
		VARIABLE TX_OUT : LINE;

		BEGIN
		-- --------------------
		reset <= transport '1';
		sdata <= transport std_logic_vector'("ZZZZZZZZZZZZZZZZ"); --Z
		-- --------------------
		WAIT FOR 100 ns; -- Time=100 ns
		reset <= transport '0';
		-- --------------------
		WAIT FOR 200 ns; -- Time=300 ns
		sdata <= transport std_logic_vector'("0100011100000000"); --4700
		-- --------------------
		WAIT FOR 100 ns; -- Time=400 ns
		sdata <= transport std_logic_vector'("ZZZZZZZZZZZZZZZZ"); --Z
		-- --------------------
		WAIT FOR 200 ns; -- Time=600 ns
		sdata <= transport std_logic_vector'("0010000001000111"); --2047
		-- --------------------
		WAIT FOR 100 ns; -- Time=700 ns
		sdata <= transport std_logic_vector'("ZZZZZZZZZZZZZZZZ"); --Z
		-- --------------------
		WAIT FOR 960 ns; -- Time=1660 ns
		-- --------------------

		STD.TEXTIO.write(TX_OUT, string'("Total[]"));
		STD.TEXTIO.writeline(results, TX_OUT);
		ASSERT (FALSE) REPORT
			"Success! Simulation for annotation completed"
			SEVERITY FAILURE;
	END PROCESS;
END testbench_arch;

CONFIGURATION sum_cfg OF pp IS
	FOR testbench_arch
	END FOR;
END sum_cfg;