sum.syr

这是一个用VHDL写的简易的CPU的程序

Top Level Output File Name         : sum
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 97

Macro Statistics :
# ROMs                             : 1
#      32x28-bit ROM               : 1
# Registers                        : 69
#      1-bit register              : 57
#      16-bit register             : 1
#      8-bit register              : 11
# Multiplexers                     : 51
#      1-bit 4-to-1 multiplexer    : 1
#      2-to-1 multiplexer          : 49
#      8-bit 16-to-1 multiplexer   : 1
# Tristates                        : 2
#      16-bit tristate buffer      : 2
# Decoders                         : 2
#      1-of-8 decoder              : 2
# Adders/Subtractors               : 2
#      16-bit adder                : 1
#      8-bit addsub                : 1

Cell Usage :
# BELS                             : 435
#      GND                         : 1
#      LUT1                        : 18
#      LUT2                        : 19
#      LUT3                        : 46
#      LUT3_D                      : 2
#      LUT3_L                      : 23
#      LUT4                        : 147
#      LUT4_D                      : 8
#      LUT4_L                      : 66
#      MUXCY                       : 22
#      MUXF5                       : 52
#      MUXF6                       : 7
#      VCC                         : 1
#      XORCY                       : 23
# FlipFlops/Latches                : 217
#      FD                          : 8
#      FDC                         : 12
#      FDC_1                       : 17
#      FDCE_1                      : 1
#      FDCPE                       : 16
#      FDCPE_1                     : 16
#      FDE_1                       : 147
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 96
#      IBUF                        : 1
#      IOBUF                       : 16
#      OBUF                        : 63
#      OBUFT                       : 16
=========================================================================

Device utilization summary:
---------------------------

Selected Device : v200pq240-4 

 Number of Slices:                     203  out of   2352     8%  
 Number of Slice Flip Flops:           217  out of   4704     4%  
 Number of 4 input LUTs:               329  out of   4704     6%  
 Number of bonded IOBs:                 96  out of    170    56%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
u1_mt0:Q                           | NONE                   | 75    |
u1_mt0_1:Q                         | NONE                   | 81    |
u1_mt1:Q                           | NONE                   | 58    |
clkg                               | BUFGP                  | 3     |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 30.584ns (Maximum Frequency: 32.697MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 21.746ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'u1_mt0:Q'
Delay:               14.742ns (Levels of Logic = 6)
  Source:            ir_0 (FF)
  Destination:       databus_7 (FF)
  Source Clock:      u1_mt0:Q falling
  Destination Clock: u1_mt0:Q rising

  Data Path: ir_0 to databus_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE_1:C->Q           12   1.372   2.640  ir_0 (ir_0)
     LUT4_D:I0->O         18   0.738   3.300  u3__n003311 (CHOICE367)
     LUT4_L:I1->LO         1   0.738   0.000  Mmux__n0013_inst_lut3_591 (Mmux__n0013__net112)
     MUXF5:I0->O           1   0.562   0.000  Mmux__n0013_inst_mux_f5_22 (Mmux__n0013__net114)
     MUXF6:I0->O           2   0.412   1.474  Mmux__n0013_inst_mux_f6_15 (Mmux__n0013__net118)
     LUT4:I3->O            1   0.738   1.265  Mmux__n0013_inst_mux_f6_14_SW1 (N10817)
     LUT3_L:I2->LO         1   0.738   0.000  Mmux__n0013_inst_lut3_631 (_n0013<7>)
     FD:D                      0.765          databus_7
    ----------------------------------------
    Total                     14.742ns (6.063ns logic, 8.679ns route)
                                       (41.1% logic, 58.9% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'u1_mt0_1:Q'
Delay:               9.532ns (Levels of Logic = 19)
  Source:            pc_0 (FF)
  Destination:       pc_15 (FF)
  Source Clock:      u1_mt0_1:Q falling
  Destination Clock: u1_mt0_1:Q falling

  Data Path: pc_0 to pc_15
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC_1:C->Q            5   1.372   1.914  pc_0 (pc_0)
     LUT1:I0->O            2   0.738   0.000  Madd__n0000_inst_lut2_01 (Madd__n0000_inst_lut2_0)
     MUXCY:S->O            1   0.842   0.000  Madd__n0000_inst_cy_8 (Madd__n0000_inst_cy_8)
     MUXCY:CI->O           1   0.057   0.000  Madd__n0000_inst_cy_9 (Madd__n0000_inst_cy_9)
     MUXCY:CI->O           1   0.057   0.000  Madd__n0000_inst_cy_10 (Madd__n0000_inst_cy_10)
     MUXCY:CI->O           1   0.057   0.000  Madd__n0000_inst_cy_11 (Madd__n0000_inst_cy_11)
     MUXCY:CI->O           1   0.057   0.000  Madd__n0000_inst_cy_12 (Madd__n0000_inst_cy_12)
     MUXCY:CI->O           1   0.057   0.000  Madd__n0000_inst_cy_13 (Madd__n0000_inst_cy_13)
     MUXCY:CI->O           1   0.057   0.000  Madd__n0000_inst_cy_14 (Madd__n0000_inst_cy_14)
     MUXCY:CI->O           1   0.057   0.000  Madd__n0000_inst_cy_15 (Madd__n0000_inst_cy_15)
     MUXCY:CI->O           1   0.057   0.000  Madd__n0000_inst_cy_16 (Madd__n0000_inst_cy_16)
     MUXCY:CI->O           1   0.057   0.000  Madd__n0000_inst_cy_17 (Madd__n0000_inst_cy_17)
     MUXCY:CI->O           1   0.057   0.000  Madd__n0000_inst_cy_18 (Madd__n0000_inst_cy_18)
     MUXCY:CI->O           1   0.057   0.000  Madd__n0000_inst_cy_19 (Madd__n0000_inst_cy_19)
     MUXCY:CI->O           1   0.057   0.000  Madd__n0000_inst_cy_20 (Madd__n0000_inst_cy_20)
     MUXCY:CI->O           1   0.057   0.000  Madd__n0000_inst_cy_21 (Madd__n0000_inst_cy_21)
     MUXCY:CI->O           0   0.057   0.000  Madd__n0000_inst_cy_22 (Madd__n0000_inst_cy_22)
     XORCY:CI->O           1   0.538   1.265  Madd__n0000_inst_sum_23 (_n0000<15>)
     LUT4:I3->O            1   0.738   0.000  Mmux__n0014_Result51_F (N11191)
     MUXF5:I0->O           1   0.562   0.000  Mmux__n0014_Result51 (_n0014)
     FDC_1:D                   0.765          pc_15
    ----------------------------------------
    Total                      9.532ns (6.353ns logic, 3.179ns route)
                                       (66.6% logic, 33.4% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'u1_mt1:Q'
Delay:               15.292ns (Levels of Logic = 3)
  Source:            u2_caddress_1 (FF)
  Destination:       Mtrien_sdata (FF)
  Source Clock:      u1_mt1:Q rising
  Destination Clock: u1_mt1:Q falling

  Data Path: u2_caddress_1 to Mtrien_sdata
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              4   1.372   1.760  u2_caddress_1 (u2_caddress_1)
     LUT3_D:I0->O          3   0.738   1.628  u2_Mrom_cdata_inst_mux_f5_33_SW0 (N10686)
     LUT4:I3->O           17   0.738   3.190  u4_readm1 (readm)
     LUT3:I2->O           32   0.738   4.180  _n01901 (_n0190)
     FDCPE_1:CE                0.948          Mtrien_sdata
    ----------------------------------------
    Total                     15.292ns (4.534ns logic, 10.758ns route)
                                       (29.6% logic, 70.4% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'clkg'
Delay:               11.180ns (Levels of Logic = 1)
  Source:            u1_mt0 (FF)
  Destination:       u1_mt0 (FF)
  Source Clock:      clkg rising
  Destination Clock: clkg rising

  Data Path: u1_mt0 to u1_mt0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q            107   1.372   8.305  u1_mt0 (u1_mt0)
     LUT1:I0->O            2   0.738   0.000  u1__n00021 (u1__n0002)
     FDC:D                     0.765          u1_mt0
    ----------------------------------------
    Total                     11.180ns (2.875ns logic, 8.305ns route)
                                       (25.7% logic, 74.3% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'u1_mt1:Q'
Offset:              21.746ns (Levels of Logic = 4)
  Source:            u2_caddress_4 (FF)
  Destination:       adress<15> (PAD)
  Source Clock:      u1_mt1:Q rising

  Data Path: u2_caddress_4 to adress<15>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q             16   1.372   3.080  u2_caddress_4 (u2_caddress_4)
     LUT2:I1->O            4   0.738   1.760  u2_Mrom_cdata_inst_mux_f5_43_SW0 (N10642)
     LUT4:I3->O           18   0.738   3.300  u4_writem1_1 (u4_writem1_1)
     LUT2:I1->O           32   0.738   4.180  _n01171 (_n0117)
     OBUFT:T->O                5.840          adress_15_OBUFT (adress<15>)
    ----------------------------------------
    Total                     21.746ns (9.426ns logic, 12.320ns route)
                                       (43.3% logic, 56.7% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'clkg'
Offset:              16.397ns (Levels of Logic = 2)
  Source:            u1_mt0_1 (FF)
  Destination:       nbh (PAD)
  Source Clock:      clkg rising

  Data Path: u1_mt0_1 to nbh
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q             90   1.372   7.370  u1_mt0_1 (u1_mt0_1)
     LUT2:I0->O            1   0.738   1.265  u4_nwr1 (nwr_OBUF)
     OBUF:I->O                 5.652          nwr_OBUF (nwr)
    ----------------------------------------
    Total                     16.397ns (7.762ns logic, 8.635ns route)
                                       (47.3% logic, 52.7% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'u1_mt0:Q'
Offset:              8.289ns (Levels of Logic = 1)
  Source:            ir_15_1 (FF)
  Destination:       sir<15> (PAD)
  Source Clock:      u1_mt0:Q falling

  Data Path: ir_15_1 to sir<15>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE_1:C->Q            1   1.372   1.265  ir_15_1 (ir_15_1)
     OBUF:I->O                 5.652          sir_15_OBUF (sir<15>)
    ----------------------------------------
    Total                      8.289ns (7.024ns logic, 1.265ns route)
                                       (84.7% logic, 15.3% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'u1_mt0_1:Q'
Offset:              8.938ns (Levels of Logic = 1)
  Source:            pc_15 (FF)
  Destination:       spc<15> (PAD)
  Source Clock:      u1_mt0_1:Q falling

  Data Path: pc_15 to spc<15>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC_1:C->Q            5   1.372   1.914  pc_15 (pc_15)
     OBUF:I->O                 5.652          spc_15_OBUF (spc<15>)
    ----------------------------------------
    Total                      8.938ns (7.024ns logic, 1.914ns route)
                                       (78.6% logic, 21.4% route)

=========================================================================
CPU : 7.11 / 7.86 s | Elapsed : 7.00 / 8.00 s
 
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Total memory usage is 69224 kilobytes