sum.syr

这是一个用VHDL写的简易的CPU的程序

Release 6.2i - xst G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
CPU : 0.00 / 0.41 s | Elapsed : 0.00 / 1.00 s
 
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 0.41 s | Elapsed : 0.00 / 1.00 s
 
--> Reading design: sum.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : sum.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : sum
Output Format                      : NGC
Target Device                      : xcv200-4-pq240

---- Source Options
Top Module Name                    : sum
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 0
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : sum.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
Optimize Instantiated Primitives   : NO
tristate2logic                     : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file D:/sum/clock.vhdl in Library work.
Architecture main of Entity clock is up to date.
Compiling vhdl file D:/sum/cu.vhd in Library work.
Architecture main of Entity cu is up to date.
Compiling vhdl file D:/sum/ieu.vhdl in Library work.
Architecture main of Entity ieu is up to date.
Compiling vhdl file D:/sum/msi.vhdl in Library work.
Architecture main of Entity msi is up to date.
Compiling vhdl file D:/sum/sum.vhdl in Library work.
Entity <sum> (Architecture <behav>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <sum> (Architecture <behav>).
WARNING:Xst:766 - D:/sum/sum.vhdl line 85: Generating a Black Box for component <bufgp>.
Entity <sum> analyzed. Unit <sum> generated.

Analyzing Entity <clock> (Architecture <main>).
Entity <clock> analyzed. Unit <clock> generated.

Analyzing Entity <cu> (Architecture <main>).
INFO:Xst:1561 - D:/sum/cu.vhd line 61: Mux is complete : default of case is discarded
WARNING:Xst:819 - D:/sum/cu.vhd line 39: The following signals are missing in the process sensitivity list:
   reset.
Entity <cu> analyzed. Unit <cu> generated.

Analyzing Entity <ieu> (Architecture <main>).
INFO:Xst:1561 - D:/sum/ieu.vhdl line 32: Mux is complete : default of case is discarded
INFO:Xst:1561 - D:/sum/ieu.vhdl line 46: Mux is complete : default of case is discarded
Entity <ieu> analyzed. Unit <ieu> generated.

Analyzing Entity <msi> (Architecture <main>).
Entity <msi> analyzed. Unit <msi> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <msi>.
    Related source file is D:/sum/msi.vhdl.
Unit <msi> synthesized.


Synthesizing Unit <ieu>.
    Related source file is D:/sum/ieu.vhdl.
    Found 1-of-8 decoder for signal <sri>.
    Found 1-of-8 decoder for signal <srj>.
    Summary:
	inferred   2 Decoder(s).
Unit <ieu> synthesized.


Synthesizing Unit <cu>.
    Related source file is D:/sum/cu.vhd.
    Found 32x28-bit ROM for signal <cdata>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0008> created at line 44.
    Found 5-bit register for signal <caddress>.
    Found 1 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   1 ROM(s).
	inferred   5 D-type flip-flop(s).
	inferred   2 Multiplexer(s).
Unit <cu> synthesized.


Synthesizing Unit <clock>.
    Related source file is D:/sum/clock.vhdl.
    Found 1-bit register for signal <mstart>.
    Found 1-bit register for signal <mt0>.
    Found 1-bit register for signal <mt1>.
    Summary:
	inferred   3 D-type flip-flop(s).
Unit <clock> synthesized.


Synthesizing Unit <sum>.
    Related source file is D:/sum/sum.vhdl.
INFO:Xst:1608 - Relative priorities of control signals on register <Mtrien_sdata> differ from those commonly found in the selected device family. This will result in additional logic around the register.
    Found 16-bit tristate buffer for signal <adress>.
    Found 16-bit tristate buffer for signal <sdata>.
    Found 16-bit adder for signal <$n0000> created at line 227.
    Found 8-bit 16-to-1 multiplexer for signal <$n0013> created at line 118.
    Found 8-bit addsub for signal <$n0097>.
    Found 8-bit register for signal <databus>.
    Found 8-bit register for signal <f1>.
    Found 8-bit register for signal <f2>.
    Found 16-bit register for signal <ir>.
    Found 16-bit register for signal <mar>.
    Found 16-bit register for signal <mdr>.
    Found 16-bit register for signal <Mtridata_sdata> created at line 272.
    Found 1-bit register for signal <Mtrien_sdata> created at line 272.
    Found 16-bit register for signal <pc>.
    Found 8-bit register for signal <reg0>.
    Found 8-bit register for signal <reg1>.
    Found 8-bit register for signal <reg2>.
    Found 8-bit register for signal <reg3>.
    Found 8-bit register for signal <reg4>.
    Found 8-bit register for signal <reg5>.
    Found 8-bit register for signal <reg6>.
    Found 8-bit register for signal <reg7>.
    Found 48 1-bit 2-to-1 multiplexers.
    Summary:
	inferred 153 D-type flip-flop(s).
	inferred   2 Adder/Subtracter(s).
	inferred  56 Multiplexer(s).
	inferred  32 Tristate(s).
Unit <sum> synthesized.

INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# ROMs                             : 1
 32x28-bit ROM                     : 1
# Adders/Subtractors               : 2
 8-bit addsub                      : 1
 16-bit adder                      : 1
# Registers                        : 70
 1-bit register                    : 57
 16-bit register                   : 2
 8-bit register                    : 11
# Multiplexers                     : 51
 1-bit 2-to-1 multiplexer          : 49
 8-bit 16-to-1 multiplexer         : 1
 1-bit 4-to-1 multiplexer          : 1
# Decoders                         : 2
 1-of-8 decoder                    : 2
# Tristates                        : 2
 16-bit tristate buffer            : 2

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <sum> ...

Optimizing unit <msi> ...

Optimizing unit <cu> ...

Optimizing unit <ieu> ...
Loading device for application Xst from file 'v200.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block sum, actual ratio is 9.
FlipFlop u2_caddress_0 has been replicated 1 time(s)
FlipFlop u2_caddress_1 has been replicated 1 time(s)
FlipFlop u2_caddress_3 has been replicated 1 time(s)
FlipFlop u2_caddress_2 has been replicated 1 time(s)
FlipFlop ir_11 has been replicated 1 time(s)
FlipFlop ir_12 has been replicated 1 time(s)
FlipFlop u2_caddress_4 has been replicated 1 time(s)
FlipFlop ir_11 has been replicated 1 time(s)
FlipFlop u1_mt0 has been replicated 1 time(s)
FlipFlop Mtrien_sdata has been replicated 15 time(s) to handle iob=true attribute.
FlipFlop ir_15 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop ir_14 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop ir_13 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop ir_12_1 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop ir_11_2 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop ir_10 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop ir_9 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop ir_8 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop ir_7 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop ir_6 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop ir_5 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop ir_4 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop ir_3 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop ir_2 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop ir_1 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop ir_0 has been replicated 1 time(s) to handle iob=true attribute.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : sum.ngr