ieu.vhdl

这是一个用VHDL写的简易的CPU的程序

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ieu is
    Port ( cri : in std_logic_vector(2 downto 0);
           crj : in std_logic_vector(2 downto 0);
           istr : in std_logic_vector(4 downto 0);
           ld: out std_logic_vector(7 downto 0);
		 	  resours:out std_logic_vector(3 downto 0));
end ieu;

architecture main of ieu is
	signal sri,srj,mld:std_logic_vector(7 downto 0);
begin
	process(cri)
	begin
		case cri is 
		when "000"=>sri<="00000001";
		when "001"=>sri<="00000010";
		when "010"=>sri<="00000100";
		when "011"=>sri<="00001000";
		when "100"=>sri<="00010000";
		when "101"=>sri<="00100000";
		when "110"=>sri<="01000000";
		when "111"=>sri<="10000000";
		when 	others=>sri<="00000000";
		end case;
	end process;
	process(crj)
	begin
		case crj is 
		when "000"=>srj<="00000001";
		when "001"=>srj<="00000010";
		when "010"=>srj<="00000100";
		when "011"=>srj<="00001000";
		when "100"=>srj<="00010000";
		when "101"=>srj<="00100000";
		when "110"=>srj<="01000000";
		when "111"=>srj<="10000000";
		when others=>srj<="00000000";
		end case;
	end process;
	process(istr,cri,crj)
	begin
		case istr(4 downto 2) is
		when "000"=>resours(3 downto 0)<="0000";
		when "001"=>resours(3)<='1';resours(2 downto 0)<=cri(2 downto 0);
		when "010"=>resours(3)<='1';resours(2 downto 0)<=crj(2 downto 0);
		when "011"=>resours(3 downto 0)<="1111";
		when others=>resours(3)<='0';resours(2 downto 0)<=istr(4 downto 2);
		end case;
	end process;

	mld(0)<=(sri(0) and istr(1))or(srj(0) and istr(0));
	mld(1)<=(sri(1) and istr(1))or(srj(1) and istr(0));
	mld(2)<=(sri(2) and istr(1))or(srj(2) and istr(0));
	mld(3)<=(sri(3) and istr(1))or(srj(3) and istr(0));
	mld(4)<=(sri(4) and istr(1))or(srj(4) and istr(0));
	mld(5)<=(sri(5) and istr(1))or(srj(5) and istr(0));
	mld(6)<=(sri(6) and istr(1))or(srj(6) and istr(0));
	mld(7)<=(sri(7) and istr(1))or(srj(7) and istr(0));


	
	ld(0)<=mld(0) ;
	ld(1)<=mld(1) ;
	ld(2)<=mld(2) ;
	ld(3)<=mld(3) ;
	ld(4)<=mld(4) ;
	ld(5)<=mld(5) ;
	ld(6)<=mld(6) ;
	ld(7)<=mld(7) ;


end main;