clock.twr

这是一个用VHDL写的简易的CPU的程序

--------------------------------------------------------------------------------
Release 6.2i Trace G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.

C:/Xilinx/bin/nt/trce.exe -intstyle ise -e 3 -l 3 -xml clock clock.ncd -o
clock.twr clock.pcf


Design file:              clock.ncd
Physical constraint file: clock.pcf
Device,speed:             xcv200,-4 (FINAL 1.123 2003-12-13)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Clock clk to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
t0          |   16.380(R)|clk_IBUF          |   0.000|
t1          |   15.463(F)|clk_IBUF          |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk            |    3.695|         |         |    3.402|
---------------+---------+---------+---------+---------+

Analysis completed Wed Nov 21 16:43:45 2007
--------------------------------------------------------------------------------

Peak Memory Usage: 50 MB