colorbar.vo

我买的红色飓风FPGA,EP1C6开发板的配套USBA实验例程 VGA模块的程序

	.padio(clk));
// synopsys translate_off
defparam \clk~I .operation_mode = "input";
defparam \clk~I .input_register_mode = "none";
defparam \clk~I .output_register_mode = "none";
defparam \clk~I .oe_register_mode = "none";
defparam \clk~I .input_async_reset = "none";
defparam \clk~I .output_async_reset = "none";
defparam \clk~I .oe_async_reset = "none";
defparam \clk~I .input_sync_reset = "none";
defparam \clk~I .output_sync_reset = "none";
defparam \clk~I .oe_sync_reset = "none";
defparam \clk~I .input_power_up = "low";
defparam \clk~I .output_power_up = "low";
defparam \clk~I .oe_power_up = "low";
// synopsys translate_on

// atom is at PLL_2
cyclone_pll \inst4|altpll_component|pll (
	.fbin(vcc),
	.ena(vcc),
	.clkswitch(gnd),
	.areset(gnd),
	.pfdena(vcc),
	.scanclk(gnd),
	.scanaclr(gnd),
	.scandata(vcc),
	.comparator(gnd),
	.inclk({gnd,\clk~combout }),
	.clkena({vcc,vcc,vcc,vcc,vcc,vcc}),
	.extclkena({vcc,vcc,vcc,vcc}),
	.activeclock(),
	.clkloss(),
	.locked(),
	.scandataout(),
	.enable0(),
	.enable1(),
	.clk(\inst4|altpll_component|pll_CLK_bus ),
	.extclk(),
	.clkbad());
// synopsys translate_off
defparam \inst4|altpll_component|pll .operation_mode = "normal";
defparam \inst4|altpll_component|pll .pll_type = "auto";
defparam \inst4|altpll_component|pll .qualify_conf_done = "off";
defparam \inst4|altpll_component|pll .valid_lock_multiplier = 1;
defparam \inst4|altpll_component|pll .invalid_lock_multiplier = 5;
defparam \inst4|altpll_component|pll .compensate_clock = "clk0";
defparam \inst4|altpll_component|pll .inclk0_input_frequency = 20000;
defparam \inst4|altpll_component|pll .inclk1_input_frequency = 20000;
defparam \inst4|altpll_component|pll .pfd_min = 5000;
defparam \inst4|altpll_component|pll .pfd_max = 66666;
defparam \inst4|altpll_component|pll .vco_min = 1000;
defparam \inst4|altpll_component|pll .vco_max = 2037;
defparam \inst4|altpll_component|pll .vco_center = 1250;
defparam \inst4|altpll_component|pll .pll_compensation_delay = 5200;
defparam \inst4|altpll_component|pll .skip_vco = "off";
defparam \inst4|altpll_component|pll .primary_clock = "inclk0";
defparam \inst4|altpll_component|pll .switch_over_on_lossclk = "off";
defparam \inst4|altpll_component|pll .switch_over_on_gated_lock = "off";
defparam \inst4|altpll_component|pll .enable_switch_over_counter = "off";
defparam \inst4|altpll_component|pll .gate_lock_signal = "no";
defparam \inst4|altpll_component|pll .gate_lock_counter = 0;
defparam \inst4|altpll_component|pll .switch_over_counter = 1;
defparam \inst4|altpll_component|pll .m = 16;
defparam \inst4|altpll_component|pll .n = 1;
defparam \inst4|altpll_component|pll .m2 = 1;
defparam \inst4|altpll_component|pll .n2 = 1;
defparam \inst4|altpll_component|pll .charge_pump_current = 40;
defparam \inst4|altpll_component|pll .loop_filter_c = 10;
defparam \inst4|altpll_component|pll .loop_filter_r = "1.021000";
defparam \inst4|altpll_component|pll .clk0_counter = "g1";
defparam \inst4|altpll_component|pll .l0_mode = "odd";
defparam \inst4|altpll_component|pll .l1_mode = "bypass";
defparam \inst4|altpll_component|pll .g0_mode = "bypass";
defparam \inst4|altpll_component|pll .g1_mode = "even";
defparam \inst4|altpll_component|pll .g2_mode = "bypass";
defparam \inst4|altpll_component|pll .g3_mode = "bypass";
defparam \inst4|altpll_component|pll .e0_mode = "bypass";
defparam \inst4|altpll_component|pll .e1_mode = "bypass";
defparam \inst4|altpll_component|pll .e2_mode = "bypass";
defparam \inst4|altpll_component|pll .e3_mode = "bypass";
defparam \inst4|altpll_component|pll .l0_high = 8;
defparam \inst4|altpll_component|pll .g1_high = 10;
defparam \inst4|altpll_component|pll .l0_low = 7;
defparam \inst4|altpll_component|pll .g1_low = 10;
defparam \inst4|altpll_component|pll .m_initial = 1;
defparam \inst4|altpll_component|pll .l0_initial = 1;
defparam \inst4|altpll_component|pll .g1_initial = 1;
defparam \inst4|altpll_component|pll .m_ph = 0;
defparam \inst4|altpll_component|pll .l0_ph = 0;
defparam \inst4|altpll_component|pll .l1_ph = 0;
defparam \inst4|altpll_component|pll .g0_ph = 0;
defparam \inst4|altpll_component|pll .g1_ph = 0;
defparam \inst4|altpll_component|pll .g2_ph = 0;
defparam \inst4|altpll_component|pll .g3_ph = 0;
defparam \inst4|altpll_component|pll .e0_ph = 0;
defparam \inst4|altpll_component|pll .e1_ph = 0;
defparam \inst4|altpll_component|pll .e2_ph = 0;
defparam \inst4|altpll_component|pll .e3_ph = 0;
defparam \inst4|altpll_component|pll .m_time_delay = 0;
defparam \inst4|altpll_component|pll .n_time_delay = 0;
defparam \inst4|altpll_component|pll .l0_time_delay = 0;
defparam \inst4|altpll_component|pll .l1_time_delay = 0;
defparam \inst4|altpll_component|pll .g0_time_delay = 0;
defparam \inst4|altpll_component|pll .g1_time_delay = 0;
defparam \inst4|altpll_component|pll .g2_time_delay = 0;
defparam \inst4|altpll_component|pll .g3_time_delay = 0;
defparam \inst4|altpll_component|pll .e0_time_delay = 0;
defparam \inst4|altpll_component|pll .e1_time_delay = 0;
defparam \inst4|altpll_component|pll .e2_time_delay = 0;
defparam \inst4|altpll_component|pll .e3_time_delay = 0;
defparam \inst4|altpll_component|pll .bandwidth_type = "auto";
defparam \inst4|altpll_component|pll .bandwidth = 1295546;
defparam \inst4|altpll_component|pll .spread_frequency = 0;
defparam \inst4|altpll_component|pll .down_spread = "0 %";
defparam \inst4|altpll_component|pll .clk0_multiply_by = 4;
defparam \inst4|altpll_component|pll .clk1_multiply_by = 1;
defparam \inst4|altpll_component|pll .clk2_multiply_by = 1;
defparam \inst4|altpll_component|pll .clk3_multiply_by = 1;
defparam \inst4|altpll_component|pll .clk4_multiply_by = 1;
defparam \inst4|altpll_component|pll .clk5_multiply_by = 1;
defparam \inst4|altpll_component|pll .extclk0_multiply_by = 1;
defparam \inst4|altpll_component|pll .extclk1_multiply_by = 1;
defparam \inst4|altpll_component|pll .extclk2_multiply_by = 1;
defparam \inst4|altpll_component|pll .extclk3_multiply_by = 1;
defparam \inst4|altpll_component|pll .clk0_divide_by = 5;
defparam \inst4|altpll_component|pll .clk1_divide_by = 1;
defparam \inst4|altpll_component|pll .clk2_divide_by = 1;
defparam \inst4|altpll_component|pll .clk3_divide_by = 1;
defparam \inst4|altpll_component|pll .clk4_divide_by = 1;
defparam \inst4|altpll_component|pll .clk5_divide_by = 1;
defparam \inst4|altpll_component|pll .extclk0_divide_by = 1;
defparam \inst4|altpll_component|pll .extclk1_divide_by = 1;
defparam \inst4|altpll_component|pll .extclk2_divide_by = 1;
defparam \inst4|altpll_component|pll .extclk3_divide_by = 1;
defparam \inst4|altpll_component|pll .clk0_phase_shift = "0";
defparam \inst4|altpll_component|pll .clk1_phase_shift = "0";
defparam \inst4|altpll_component|pll .clk2_phase_shift = "0";
defparam \inst4|altpll_component|pll .clk3_phase_shift = "0";
defparam \inst4|altpll_component|pll .clk4_phase_shift = "0";
defparam \inst4|altpll_component|pll .clk5_phase_shift = "0";
defparam \inst4|altpll_component|pll .extclk0_phase_shift = "0";
defparam \inst4|altpll_component|pll .extclk1_phase_shift = "0";
defparam \inst4|altpll_component|pll .extclk2_phase_shift = "0";
defparam \inst4|altpll_component|pll .extclk3_phase_shift = "0";
defparam \inst4|altpll_component|pll .clk0_time_delay = "0";
defparam \inst4|altpll_component|pll .clk1_time_delay = "0";
defparam \inst4|altpll_component|pll .clk2_time_delay = "0";
defparam \inst4|altpll_component|pll .clk3_time_delay = "0";
defparam \inst4|altpll_component|pll .clk4_time_delay = "0";
defparam \inst4|altpll_component|pll .clk5_time_delay = "0";
defparam \inst4|altpll_component|pll .extclk0_time_delay = "0";
defparam \inst4|altpll_component|pll .extclk1_time_delay = "0";
defparam \inst4|altpll_component|pll .extclk2_time_delay = "0";
defparam \inst4|altpll_component|pll .extclk3_time_delay = "0";
defparam \inst4|altpll_component|pll .clk0_duty_cycle = 50;
defparam \inst4|altpll_component|pll .clk1_duty_cycle = 50;
defparam \inst4|altpll_component|pll .clk2_duty_cycle = 50;
defparam \inst4|altpll_component|pll .clk3_duty_cycle = 50;
defparam \inst4|altpll_component|pll .clk4_duty_cycle = 50;
defparam \inst4|altpll_component|pll .clk5_duty_cycle = 50;
defparam \inst4|altpll_component|pll .extclk0_duty_cycle = 50;
defparam \inst4|altpll_component|pll .extclk1_duty_cycle = 50;
defparam \inst4|altpll_component|pll .extclk2_duty_cycle = 50;
defparam \inst4|altpll_component|pll .extclk3_duty_cycle = 50;
defparam \inst4|altpll_component|pll .simulation_type = "timing";
// synopsys translate_on

// atom is at PIN_131
cyclone_io \rst~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\rst~combout ),
	.regout(),
	.padio(rst));
// synopsys translate_off
defparam \rst~I .operation_mode = "input";
defparam \rst~I .input_register_mode = "none";
defparam \rst~I .output_register_mode = "none";
defparam \rst~I .oe_register_mode = "none";
defparam \rst~I .input_async_reset = "none";
defparam \rst~I .output_async_reset = "none";
defparam \rst~I .oe_async_reset = "none";
defparam \rst~I .input_sync_reset = "none";
defparam \rst~I .output_sync_reset = "none";
defparam \rst~I .oe_sync_reset = "none";
defparam \rst~I .input_power_up = "low";
defparam \rst~I .output_power_up = "low";
defparam \rst~I .oe_power_up = "low";
// synopsys translate_on

// atom is at LC_X16_Y14_N5
cyclone_lcell \inst|hcnt[0]~I (
// Equation(s):
// \inst|hcnt[0]  = DFFEAS(!\inst|hcnt[0] , GLOBAL(\inst4|altpll_component|_clk0 ), GLOBAL(\rst~combout ), , , , , \inst|LessThan~1887 , )
// \inst|hcnt[0]~430  = CARRY(\inst|hcnt[0] )
// \inst|hcnt[0]~430COUT1_447  = CARRY(\inst|hcnt[0] )

	.clk(\inst4|altpll_component|_clk0 ),
	.dataa(vcc),
	.datab(\inst|hcnt[0] ),
	.datac(vcc),
	.datad(vcc),
	.aclr(!\rst~combout ),
	.aload(gnd),