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我买的红色飓风FPGA,EP1C6开发板的配套USBA实验例程 VGA模块的程序

wire \auto_signaltap_0|ela_control|\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|\trigger_modules_gen:0:trigger_match|\gen_sbpmg_pipeline_less_than_two:sm0:3:sm1|holdff ;
wire \auto_signaltap_0|ela_control|\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|\trigger_modules_gen:0:trigger_match|\gen_sbpmg_pipeline_less_than_two:sm0:3:sm1|p_match_out~206 ;
wire \auto_signaltap_0|ela_control|\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|\trigger_modules_gen:0:trigger_match|\gen_sbpmg_pipeline_less_than_two:sm0:3:sm1|match_out ;
wire \auto_signaltap_0|ela_control|ela_level_seq_mgr|trigger_happened~116 ;
wire \auto_signaltap_0|ela_control|ela_level_seq_mgr|trigger_happened~117 ;
wire \auto_signaltap_0|ela_control|ela_level_seq_mgr|trigger_happened_ff[1] ;
wire \auto_signaltap_0|ela_control|ela_level_seq_mgr|trigger_happened~118 ;
wire \sld_hub_inst|IRSR|Q[6] ;
wire \sld_hub_inst|IRSR|Q[5] ;
wire \sld_hub_inst|IRSR|Q[4] ;
wire \sld_hub_inst|IRSR|Q[3] ;
wire \sld_hub_inst|instruction_decoder|auto_generated|dffe1a[1] ;
wire \auto_signaltap_0|sdr~13 ;
wire \auto_signaltap_0|crc_rom_sr|word_counter[0]~6 ;
wire \auto_signaltap_0|crc_rom_sr|word_counter[2]~210 ;
wire \auto_signaltap_0|crc_rom_sr|word_counter[2] ;
wire \auto_signaltap_0|crc_rom_sr|word_counter[3] ;
wire \auto_signaltap_0|crc_rom_sr|reduce_nor~3 ;
wire \auto_signaltap_0|crc_rom_sr|word_counter[0] ;
wire \auto_signaltap_0|crc_rom_sr|word_counter[1]~212 ;
wire \auto_signaltap_0|crc_rom_sr|word_counter[1] ;
wire \auto_signaltap_0|crc_rom_sr|WORD_SR~426 ;
wire \auto_signaltap_0|crc_rom_sr|WORD_SR~431 ;
wire \auto_signaltap_0|comb~26 ;
wire \auto_signaltap_0|crc_rom_sr|WORD_SR[3] ;
wire \auto_signaltap_0|crc_rom_sr|WORD_SR~429 ;
wire \auto_signaltap_0|crc_rom_sr|WORD_SR[2] ;
wire \auto_signaltap_0|crc_rom_sr|WORD_SR[1] ;
wire \auto_signaltap_0|crc_rom_sr|WORD_SR[0] ;
wire \sld_hub_inst|\GEN_SHADOW_IRF:1:S_IRF|Q[5] ;
wire \sld_hub_inst|\GEN_IRF:1:IRF|Q[5] ;
wire \sld_hub_inst|\GEN_SHADOW_IRF:1:S_IRF|Q[4] ;
wire \sld_hub_inst|\GEN_IRF:1:IRF|Q[4] ;
wire \auto_signaltap_0|ela_control|trigger_config_deserialize|dffs[2] ;
wire \auto_signaltap_0|ela_control|trigger_config_deserialize|dffs[1] ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|trigger_write_addr_latch_ena~51 ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\gen_non_zero_sample_depth:trigger_address_register|dffs[3] ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\gen_non_zero_sample_depth:trigger_address_register|dffs[6] ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\gen_non_zero_sample_depth:trigger_address_register|dffs[8] ;
wire \altera_internal_jtag~TCKUTAP ;
wire \auto_signaltap_0|ela_control|buffer_write_ena_int~42 ;
wire \auto_signaltap_0|acq_data_in_pipe_reg[2][0] ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|acq_buf_read_reset~29 ;
wire \~GND ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|offload_shift_ena ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|\adv_point_3_and_more:advance_pointer_counter|auto_generated|safe_q[0] ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|\adv_point_3_and_more:advance_pointer_counter|auto_generated|counter_cella0~COUT ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|\adv_point_3_and_more:advance_pointer_counter|auto_generated|counter_cella0~COUTCOUT1_19 ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|\adv_point_3_and_more:advance_pointer_counter|auto_generated|counter_cella1~COUT ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|\adv_point_3_and_more:advance_pointer_counter|auto_generated|counter_cella1~COUTCOUT1_16 ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|\adv_point_3_and_more:advance_pointer_counter|auto_generated|safe_q[2] ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|reduce_nor~1 ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|\adv_point_3_and_more:advance_pointer_counter|auto_generated|counter_cella2~COUT ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|\adv_point_3_and_more:advance_pointer_counter|auto_generated|counter_cella2~COUTCOUT1_18 ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|\adv_point_3_and_more:advance_pointer_counter|auto_generated|modulus_trigger ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|\adv_point_3_and_more:advance_pointer_counter|auto_generated|safe_q[1] ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|reduce_nor~0 ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|read_pointer_counter|auto_generated|safe_q[0] ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|read_pointer_counter|auto_generated|counter_cella0~COUT ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|read_pointer_counter|auto_generated|counter_cella0~COUTCOUT1_3 ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|read_pointer_counter|auto_generated|safe_q[1] ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|read_pointer_counter|auto_generated|counter_cella1~COUT ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|read_pointer_counter|auto_generated|counter_cella1~COUTCOUT1_3 ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|read_pointer_counter|auto_generated|safe_q[2] ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|read_pointer_counter|auto_generated|counter_cella2~COUT ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|read_pointer_counter|auto_generated|counter_cella2~COUTCOUT1_3 ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|read_pointer_counter|auto_generated|safe_q[3] ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|read_pointer_counter|auto_generated|counter_cella3~COUT ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|read_pointer_counter|auto_generated|counter_cella3~COUTCOUT1_3 ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|read_pointer_counter|auto_generated|safe_q[4] ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|read_pointer_counter|auto_generated|counter_cella4~COUT ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|read_pointer_counter|auto_generated|safe_q[5] ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|read_pointer_counter|auto_generated|counter_cella5~COUT ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|read_pointer_counter|auto_generated|counter_cella5~COUTCOUT1_3 ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|read_pointer_counter|auto_generated|safe_q[6] ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|read_pointer_counter|auto_generated|counter_cella6~COUT ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|read_pointer_counter|auto_generated|counter_cella6~COUTCOUT1_3 ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|read_pointer_counter|auto_generated|safe_q[7] ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|read_pointer_counter|auto_generated|counter_cella7~COUT ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|read_pointer_counter|auto_generated|counter_cella7~COUTCOUT1_3 ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|read_pointer_counter|auto_generated|safe_q[8] ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|read_pointer_counter|auto_generated|counter_cella8~COUT ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|read_pointer_counter|auto_generated|counter_cella8~COUTCOUT1_3 ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|read_pointer_counter|auto_generated|safe_q[9] ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|read_pointer_counter|auto_generated|counter_cella9~COUT ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|read_pointer_counter|auto_generated|safe_q[10] ;
wire \auto_signaltap_0|acq_data_in_pipe_reg[2][1] ;
wire \auto_signaltap_0|\stp_non_zero_ram_gen:stp_buffer_ram|auto_generated|q_b[0] ;
wire \auto_signaltap_0|acq_data_in_pipe_reg[2][2] ;
wire \auto_signaltap_0|acq_data_in_pipe_reg[2][5] ;
wire \auto_signaltap_0|\stp_non_zero_ram_gen:stp_buffer_ram|auto_generated|q_b[2] ;
wire \auto_signaltap_0|\stp_non_zero_ram_gen:stp_buffer_ram|auto_generated|q_b[5] ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|ram_data_shift_out|dffs[5] ;
wire \auto_signaltap_0|acq_data_in_pipe_reg[2][3] ;
wire \auto_signaltap_0|acq_data_in_pipe_reg[2][4] ;
wire \auto_signaltap_0|\stp_non_zero_ram_gen:stp_buffer_ram|auto_generated|q_b[4] ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|ram_data_shift_out|dffs[4] ;
wire \auto_signaltap_0|\stp_non_zero_ram_gen:stp_buffer_ram|auto_generated|q_b[3] ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|ram_data_shift_out|dffs[3] ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|ram_data_shift_out|dffs[2] ;
wire \auto_signaltap_0|\stp_non_zero_ram_gen:stp_buffer_ram|auto_generated|q_b[1] ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|ram_data_shift_out|dffs[1] ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|ram_data_shift_out|dffs[0] ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\gen_non_zero_sample_depth:trigger_address_register|dffs[10] ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|info_data_shift_out|dffs[22] ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\gen_non_zero_sample_depth:trigger_address_register|dffs[9] ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|info_data_shift_out|dffs[21] ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|info_data_shift_out|dffs[20] ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\gen_non_zero_sample_depth:trigger_address_register|dffs[7] ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|info_data_shift_out|dffs[19] ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|info_data_shift_out|dffs[18] ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\gen_non_zero_sample_depth:trigger_address_register|dffs[5] ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|info_data_shift_out|dffs[17] ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\gen_non_zero_sample_depth:trigger_address_register|dffs[4] ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|info_data_shift_out|dffs[16] ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|info_data_shift_out|dffs[15] ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\gen_non_zero_sample_depth:trigger_address_register|dffs[2] ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|info_data_shift_out|dffs[14] ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\gen_non_zero_sample_depth:trigger_address_register|dffs[1] ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|info_data_shift_out|dffs[13] ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\gen_non_zero_sample_depth:trigger_address_register|dffs[0] ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|info_data_shift_out|dffs[12] ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|info_data_shift_out|dffs[11] ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|info_data_shift_out|dffs[10] ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|info_data_shift_out|dffs[9] ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|info_data_shift_out|dffs[8] ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|info_data_shift_out|dffs[7] ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|info_data_shift_out|dffs[6] ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|info_data_shift_out|dffs[5] ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|info_data_shift_out|dffs[4] ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|info_data_shift_out|dffs[3] ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|info_data_shift_out|dffs[2] ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|info_data_shift_out|dffs[1] ;
wire \auto_signaltap_0|\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|info_data_shift_out|dffs[0] ;
wire \sld_hub_inst|hub_tdo~275 ;
wire \sld_hub_inst|IRF_ENA|Q[0] ;
wire \sld_hub_inst|node_ena~18 ;
wire \sld_hub_inst|hub_tdo~273 ;
wire \sld_hub_inst|hub_tdo~274 ;
wire \sld_hub_inst|HUB_INFO_REG|add~96 ;
wire \sld_hub_inst|HUB_INFO_REG|word_counter[0]~8 ;
wire \sld_hub_inst|HUB_INFO_REG|word_counter[0] ;
wire \sld_hub_inst|HUB_INFO_REG|add~98 ;
wire \sld_hub_inst|HUB_INFO_REG|add~98COUT1_106 ;
wire \sld_hub_inst|HUB_INFO_REG|add~81 ;
wire \sld_hub_inst|HUB_INFO_REG|word_counter[1] ;
wire \sld_hub_inst|HUB_INFO_REG|add~83 ;
wire \sld_hub_inst|HUB_INFO_REG|add~83COUT1_107 ;
wire \sld_hub_inst|HUB_INFO_REG|add~88 ;
wire \sld_hub_inst|HUB_INFO_REG|add~88COUT1_109 ;
wire \sld_hub_inst|HUB_INFO_REG|add~91 ;
wire \sld_hub_inst|HUB_INFO_REG|word_counter[3] ;
wire \sld_hub_inst|HUB_INFO_REG|add~86 ;
wire \sld_hub_inst|HUB_INFO_REG|word_counter[2] ;
wire \sld_hub_inst|HUB_INFO_REG|reduce_nor~26 ;
wire \sld_hub_inst|HUB_INFO_REG|add~93 ;
wire \sld_hub_inst|HUB_INFO_REG|add~93COUT1_111 ;
wire \sld_hub_inst|HUB_INFO_REG|add~76 ;
wire \sld_hub_inst|HUB_INFO_REG|word_counter[4] ;
wire \sld_hub_inst|HUB_INFO_REG|WORD_SR~137 ;
wire \sld_hub_inst|HUB_INFO_REG|WORD_SR~138 ;
wire \sld_hub_inst|HUB_INFO_REG|WORD_SR~140 ;
wire \sld_hub_inst|HUB_INFO_REG|WORD_SR~139 ;
wire \sld_hub_inst|HUB_INFO_REG|WORD_SR~141 ;
wire \sld_hub_inst|comb~8 ;
wire \sld_hub_inst|HUB_INFO_REG|WORD_SR[3] ;
wire \sld_hub_inst|HUB_INFO_REG|WORD_SR[2] ;
wire \sld_hub_inst|HUB_INFO_REG|WORD_SR[1] ;
wire \sld_hub_inst|HUB_INFO_REG|WORD_SR[0] ;
wire \sld_hub_inst|HUB_BYPASS_REG~18 ;
wire \sld_hub_inst|instruction_decoder|auto_generated|dffe1a[0] ;
wire \sld_hub_inst|hub_tdo~276 ;
wire \sld_hub_inst|hub_tdo~278 ;
wire \sld_hub_inst|hub_tdo~279 ;
wire \sld_hub_inst|jtag_state_machine|state~13 ;
wire \sld_hub_inst|hub_tdo ;
wire \altera_internal_jtag~TDO ;

wire [5:0] \inst4|altpll_component|pll_CLK_bus ;
wire [1:0] \auto_signaltap_0|\stp_non_zero_ram_gen:stp_buffer_ram|auto_generated|ram_block1a0_PORTBDATAOUT_bus ;
wire [1:0] \auto_signaltap_0|\stp_non_zero_ram_gen:stp_buffer_ram|auto_generated|ram_block1a2_PORTBDATAOUT_bus ;
wire [1:0] \auto_signaltap_0|\stp_non_zero_ram_gen:stp_buffer_ram|auto_generated|ram_block1a3_PORTBDATAOUT_bus ;

assign \inst4|altpll_component|_clk0  = \inst4|altpll_component|pll_CLK_bus [0];
assign \inst4|altpll_component|_clk1  = \inst4|altpll_component|pll_CLK_bus [1];
assign \inst4|altpll_component|_clk2  = \inst4|altpll_component|pll_CLK_bus [2];
assign \inst4|altpll_component|_clk3  = \inst4|altpll_component|pll_CLK_bus [3];
assign \inst4|altpll_component|_clk4  = \inst4|altpll_component|pll_CLK_bus [4];
assign \inst4|altpll_component|_clk5  = \inst4|altpll_component|pll_CLK_bus [5];

assign \auto_signaltap_0|\stp_non_zero_ram_gen:stp_buffer_ram|auto_generated|q_b[0]  = \auto_signaltap_0|\stp_non_zero_ram_gen:stp_buffer_ram|auto_generated|ram_block1a0_PORTBDATAOUT_bus [0];
assign \auto_signaltap_0|\stp_non_zero_ram_gen:stp_buffer_ram|auto_generated|q_b[1]  = \auto_signaltap_0|\stp_non_zero_ram_gen:stp_buffer_ram|auto_generated|ram_block1a0_PORTBDATAOUT_bus [1];

assign \auto_signaltap_0|\stp_non_zero_ram_gen:stp_buffer_ram|auto_generated|q_b[2]  = \auto_signaltap_0|\stp_non_zero_ram_gen:stp_buffer_ram|auto_generated|ram_block1a2_PORTBDATAOUT_bus [0];
assign \auto_signaltap_0|\stp_non_zero_ram_gen:stp_buffer_ram|auto_generated|q_b[5]  = \auto_signaltap_0|\stp_non_zero_ram_gen:stp_buffer_ram|auto_generated|ram_block1a2_PORTBDATAOUT_bus [1];

assign \auto_signaltap_0|\stp_non_zero_ram_gen:stp_buffer_ram|auto_generated|q_b[3]  = \auto_signaltap_0|\stp_non_zero_ram_gen:stp_buffer_ram|auto_generated|ram_block1a3_PORTBDATAOUT_bus [0];
assign \auto_signaltap_0|\stp_non_zero_ram_gen:stp_buffer_ram|auto_generated|q_b[4]  = \auto_signaltap_0|\stp_non_zero_ram_gen:stp_buffer_ram|auto_generated|ram_block1a3_PORTBDATAOUT_bus [1];

// atom is at PIN_153
cyclone_io \clk~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\clk~combout ),
	.regout(),