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我买的红色飓风FPGA,EP1C6开发板的配套USBA实验例程 VGA模块的程序

wire \auto_signaltap_0|crc_rom_sr|clear_signal ;
wire \auto_signaltap_0|acq_trigger_in_reg[4] ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|is_buffer_wrapped~0 ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth:tc1|post_trigger_counter|auto_generated|counter_cella0 ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth:tc1|post_trigger_counter|auto_generated|counter_cella0~COUT ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth:tc1|post_trigger_counter|auto_generated|counter_cella0~COUTCOUT1_5 ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth:tc1|post_trigger_counter|auto_generated|counter_cella1 ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth:tc1|post_trigger_counter|auto_generated|counter_cella1~COUT ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth:tc1|post_trigger_counter|auto_generated|counter_cella1~COUTCOUT1_4 ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth:tc1|post_trigger_counter|auto_generated|counter_cella2 ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth:tc1|post_trigger_counter|auto_generated|counter_cella2~COUT ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth:tc1|post_trigger_counter|auto_generated|counter_cella2~COUTCOUT1_4 ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth:tc1|post_trigger_counter|auto_generated|counter_cella3 ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth:tc1|post_trigger_counter|auto_generated|counter_cella3~COUT ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth:tc1|post_trigger_counter|auto_generated|counter_cella3~COUTCOUT1_4 ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth:tc1|post_trigger_counter|auto_generated|counter_cella4 ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth:tc1|post_trigger_counter|auto_generated|counter_cella4~COUT ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth:tc1|post_trigger_counter|auto_generated|counter_cella5 ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth:tc1|post_trigger_counter|auto_generated|counter_cella5~COUT ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth:tc1|post_trigger_counter|auto_generated|counter_cella5~COUTCOUT1_4 ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth:tc1|post_trigger_counter|auto_generated|counter_cella6 ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth:tc1|post_trigger_counter|auto_generated|counter_cella6~COUT ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth:tc1|post_trigger_counter|auto_generated|counter_cella6~COUTCOUT1_4 ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth:tc1|post_trigger_counter|auto_generated|counter_cella7 ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth:tc1|post_trigger_counter|auto_generated|counter_cella7~COUT ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth:tc1|post_trigger_counter|auto_generated|counter_cella7~COUTCOUT1_4 ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth:tc1|post_trigger_counter|auto_generated|counter_cella8 ;
wire \sld_hub_inst|jtag_debug_mode_usr0 ;
wire \sld_hub_inst|jtag_debug_mode~2 ;
wire \sld_hub_inst|jtag_debug_mode~171 ;
wire \sld_hub_inst|jtag_debug_mode ;
wire \sld_hub_inst|process2~0 ;
wire \sld_hub_inst|OK_TO_UPDATE_IR_Q ;
wire \sld_hub_inst|comb~6 ;
wire \sld_hub_inst|CLEAR_SIGNAL~0 ;
wire \sld_hub_inst|comb~68 ;
wire \sld_hub_inst|IRF_ENA_ENABLE~21 ;
wire \sld_hub_inst|IRF_ENA_0|Q[0] ;
wire \auto_signaltap_0|ela_control|sm2|status_out[1] ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|trigger_write_addr_latch_ena~50 ;
wire \sld_hub_inst|IRSR_ENA ;
wire \sld_hub_inst|IRSR|Q[7] ;
wire \sld_hub_inst|comb~66 ;
wire \sld_hub_inst|comb~67 ;
wire \sld_hub_inst|instruction_decoder|auto_generated|dffe1a[3] ;
wire \sld_hub_inst|IRSR|Q[0]~117 ;
wire \sld_hub_inst|IRSR|Q[0]~118 ;
wire \sld_hub_inst|IRSR|Q[1] ;
wire \sld_hub_inst|instruction_decoder|auto_generated|dffe1a[2] ;
wire \sld_hub_inst|BROADCAST_ENA~27 ;
wire \sld_hub_inst|BROADCAST|Q[0] ;
wire \sld_hub_inst|GEN_SHADOW_IRF~0 ;
wire \sld_hub_inst|\GEN_SHADOW_IRF:1:S_IRF|Q[1] ;
wire \sld_hub_inst|IRF_ENABLE[1]~76 ;
wire \sld_hub_inst|IRF_ENABLE[1]~77 ;
wire \sld_hub_inst|\GEN_IRF:1:IRF|Q[1] ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth:tc1|post_trigger_counter|auto_generated|counter_cella8~COUT ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth:tc1|post_trigger_counter|auto_generated|counter_cella8~COUTCOUT1_4 ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth:tc1|post_trigger_counter|auto_generated|counter_cella9 ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth:tc1|post_trigger_counter|auto_generated|counter_cella9~COUT ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth:tc1|post_trigger_counter|auto_generated|counter_cella10 ;
wire \sld_hub_inst|\GEN_SHADOW_IRF:1:S_IRF|Q[3] ;
wire \sld_hub_inst|\GEN_IRF:1:IRF|Q[3] ;
wire \auto_signaltap_0|ela_control|trigger_setup_ena ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth:tc1|stop_acquisition~100 ;
wire \auto_signaltap_0|ela_control|sm1|ela_done ;
wire \auto_signaltap_0|ela_control|trigger_config_deserialize|dffs[3] ;
wire \auto_signaltap_0|ela_control|trigger_config_deserialize|dffs[4] ;
wire \auto_signaltap_0|ela_control|sm1|edq~69 ;
wire \auto_signaltap_0|ela_control|sm1|buffer_write_enable ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth_segment:seg_mgr|\non_zero_sample_depth_gen:segment_addr_counter|auto_generated|safe_q[0] ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth_segment:seg_mgr|\non_zero_sample_depth_gen:segment_addr_counter|auto_generated|counter_cella0~COUT ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth_segment:seg_mgr|\non_zero_sample_depth_gen:segment_addr_counter|auto_generated|counter_cella0~COUTCOUT1_5 ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth_segment:seg_mgr|\non_zero_sample_depth_gen:segment_addr_counter|auto_generated|safe_q[1] ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth_segment:seg_mgr|\non_zero_sample_depth_gen:segment_addr_counter|auto_generated|counter_cella1~COUT ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth_segment:seg_mgr|\non_zero_sample_depth_gen:segment_addr_counter|auto_generated|counter_cella1~COUTCOUT1_4 ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth_segment:seg_mgr|\non_zero_sample_depth_gen:segment_addr_counter|auto_generated|safe_q[2] ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth_segment:seg_mgr|\non_zero_sample_depth_gen:segment_addr_counter|auto_generated|counter_cella2~COUT ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth_segment:seg_mgr|\non_zero_sample_depth_gen:segment_addr_counter|auto_generated|counter_cella2~COUTCOUT1_4 ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth_segment:seg_mgr|\non_zero_sample_depth_gen:segment_addr_counter|auto_generated|safe_q[3] ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth_segment:seg_mgr|\non_zero_sample_depth_gen:segment_addr_counter|auto_generated|counter_cella3~COUT ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth_segment:seg_mgr|\non_zero_sample_depth_gen:segment_addr_counter|auto_generated|counter_cella3~COUTCOUT1_4 ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth_segment:seg_mgr|\non_zero_sample_depth_gen:segment_addr_counter|auto_generated|safe_q[4] ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth_segment:seg_mgr|\non_zero_sample_depth_gen:segment_addr_counter|auto_generated|counter_cella4~COUT ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth_segment:seg_mgr|\non_zero_sample_depth_gen:segment_addr_counter|auto_generated|safe_q[5] ;
wire \auto_signaltap_0|acq_trigger_in_reg[1] ;
wire \auto_signaltap_0|acq_trigger_in_reg[3] ;
wire \auto_signaltap_0|ela_control|\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|trigger_condition_deserialize|dffs[12] ;
wire \auto_signaltap_0|ela_control|\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|trigger_condition_deserialize|dffs[11] ;
wire \auto_signaltap_0|ela_control|\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|trigger_condition_deserialize|dffs[10] ;
wire \auto_signaltap_0|ela_control|\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|trigger_condition_deserialize|dffs[9] ;
wire \auto_signaltap_0|ela_control|\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|trigger_condition_deserialize|dffs[8] ;
wire \auto_signaltap_0|ela_control|\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|trigger_condition_deserialize|dffs[7] ;
wire \auto_signaltap_0|acq_trigger_in_reg[2] ;
wire \auto_signaltap_0|ela_control|\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|trigger_condition_deserialize|dffs[6] ;
wire \auto_signaltap_0|ela_control|\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|trigger_condition_deserialize|dffs[5] ;
wire \auto_signaltap_0|ela_control|\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|trigger_condition_deserialize|dffs[4] ;
wire \auto_signaltap_0|ela_control|\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|trigger_condition_deserialize|dffs[3] ;
wire \auto_signaltap_0|ela_control|\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|trigger_condition_deserialize|dffs[2] ;
wire \auto_signaltap_0|ela_control|\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|trigger_condition_deserialize|dffs[1] ;
wire \auto_signaltap_0|acq_trigger_in_reg[0] ;
wire \auto_signaltap_0|ela_control|\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|trigger_condition_deserialize|dffs[0] ;
wire \auto_signaltap_0|ela_control|trigger_config_deserialize|dffs[19] ;
wire \auto_signaltap_0|ela_control|trigger_config_deserialize|dffs[18] ;
wire \auto_signaltap_0|ela_control|trigger_config_deserialize|dffs[17] ;
wire \auto_signaltap_0|ela_control|trigger_config_deserialize|dffs[16] ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth_segment:seg_mgr|\non_zero_sample_depth_gen:segment_addr_counter|auto_generated|counter_cella5~COUT ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth_segment:seg_mgr|\non_zero_sample_depth_gen:segment_addr_counter|auto_generated|counter_cella5~COUTCOUT1_4 ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth_segment:seg_mgr|\non_zero_sample_depth_gen:segment_addr_counter|auto_generated|safe_q[6] ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth_segment:seg_mgr|\non_zero_sample_depth_gen:segment_addr_counter|auto_generated|counter_cella6~COUT ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth_segment:seg_mgr|\non_zero_sample_depth_gen:segment_addr_counter|auto_generated|counter_cella6~COUTCOUT1_4 ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth_segment:seg_mgr|\non_zero_sample_depth_gen:segment_addr_counter|auto_generated|safe_q[7] ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth_segment:seg_mgr|\non_zero_sample_depth_gen:segment_addr_counter|auto_generated|counter_cella7~COUT ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth_segment:seg_mgr|\non_zero_sample_depth_gen:segment_addr_counter|auto_generated|counter_cella7~COUTCOUT1_4 ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth_segment:seg_mgr|\non_zero_sample_depth_gen:segment_addr_counter|auto_generated|safe_q[8] ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth_segment:seg_mgr|\non_zero_sample_depth_gen:segment_addr_counter|auto_generated|counter_cella8~COUT ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth_segment:seg_mgr|\non_zero_sample_depth_gen:segment_addr_counter|auto_generated|counter_cella8~COUTCOUT1_4 ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth_segment:seg_mgr|\non_zero_sample_depth_gen:segment_addr_counter|auto_generated|safe_q[9] ;
wire \auto_signaltap_0|ela_control|trigger_config_deserialize|dffs[15] ;
wire \auto_signaltap_0|ela_control|trigger_config_deserialize|dffs[14] ;
wire \auto_signaltap_0|ela_control|trigger_config_deserialize|dffs[13] ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth_segment:seg_mgr|\non_zero_sample_depth_gen:segment_addr_counter|auto_generated|counter_cella9~COUT ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth_segment:seg_mgr|\non_zero_sample_depth_gen:segment_addr_counter|auto_generated|safe_q[10] ;
wire \auto_signaltap_0|ela_control|trigger_config_deserialize|dffs[12] ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth_segment:seg_mgr|\non_zero_sample_depth_gen:segment_addr_compare|comparator|cmp_end|comp|sub_comptree|sub_comptree|cmp_end|aeb_out~76 ;
wire \auto_signaltap_0|ela_control|trigger_config_deserialize|dffs[11] ;
wire \auto_signaltap_0|ela_control|trigger_config_deserialize|dffs[10] ;
wire \auto_signaltap_0|ela_control|trigger_config_deserialize|dffs[9] ;
wire \auto_signaltap_0|ela_control|trigger_config_deserialize|dffs[8] ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth_segment:seg_mgr|\non_zero_sample_depth_gen:segment_addr_compare|comparator|cmp_end|comp|sub_comptree|sub_comptree|cmp_end|aeb_out~74 ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth_segment:seg_mgr|\non_zero_sample_depth_gen:segment_addr_compare|comparator|cmp_end|comp|sub_comptree|sub_comptree|cmp_end|aeb_out~71 ;
wire \auto_signaltap_0|ela_control|trigger_config_deserialize|dffs[7] ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth_segment:seg_mgr|\non_zero_sample_depth_gen:segment_addr_compare|comparator|cmp_end|comp|sub_comptree|sub_comptree|cmp_end|aeb_out~72 ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth_segment:seg_mgr|\non_zero_sample_depth_gen:segment_addr_compare|comparator|cmp_end|comp|sub_comptree|sub_comptree|cmp_end|aeb_out~73 ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth_segment:seg_mgr|\non_zero_sample_depth_gen:segment_addr_compare|comparator|cmp_end|comp|sub_comptree|sub_comptree|cmp_end|aeb_out~75 ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth_segment:seg_mgr|\non_zero_sample_depth_gen:segment_addr_compare|comparator|cmp_end|comp|sub_comptree|sub_comptree|cmp_end|aeb_out~0 ;
wire \auto_signaltap_0|ela_control|\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena ;
wire \auto_signaltap_0|ela_control|buffer_write_addr_adv_ena_int~53 ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\write_address_non_zero_gen:write_pointer_counter|auto_generated|safe_q[0] ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\write_address_non_zero_gen:write_pointer_counter|auto_generated|counter_cella0~COUT ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\write_address_non_zero_gen:write_pointer_counter|auto_generated|safe_q[1] ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\write_address_non_zero_gen:write_pointer_counter|auto_generated|counter_cella1~COUT ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\write_address_non_zero_gen:write_pointer_counter|auto_generated|counter_cella1~COUTCOUT1_3 ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\write_address_non_zero_gen:write_pointer_counter|auto_generated|safe_q[2] ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\write_address_non_zero_gen:write_pointer_counter|auto_generated|counter_cella2~COUT ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\write_address_non_zero_gen:write_pointer_counter|auto_generated|counter_cella2~COUTCOUT1_3 ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\write_address_non_zero_gen:write_pointer_counter|auto_generated|safe_q[3] ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\write_address_non_zero_gen:write_pointer_counter|auto_generated|counter_cella3~COUT ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\write_address_non_zero_gen:write_pointer_counter|auto_generated|counter_cella3~COUTCOUT1_3 ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\write_address_non_zero_gen:write_pointer_counter|auto_generated|safe_q[4] ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\write_address_non_zero_gen:write_pointer_counter|auto_generated|counter_cella4~COUT ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\write_address_non_zero_gen:write_pointer_counter|auto_generated|counter_cella4~COUTCOUT1_3 ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\write_address_non_zero_gen:write_pointer_counter|auto_generated|safe_q[5] ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\write_address_non_zero_gen:write_pointer_counter|auto_generated|counter_cella5~COUT ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\write_address_non_zero_gen:write_pointer_counter|auto_generated|safe_q[6] ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\write_address_non_zero_gen:write_pointer_counter|auto_generated|counter_cella6~COUT ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\write_address_non_zero_gen:write_pointer_counter|auto_generated|counter_cella6~COUTCOUT1_3 ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\write_address_non_zero_gen:write_pointer_counter|auto_generated|safe_q[7] ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\write_address_non_zero_gen:write_pointer_counter|auto_generated|counter_cella7~COUT ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\write_address_non_zero_gen:write_pointer_counter|auto_generated|counter_cella7~COUTCOUT1_3 ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\write_address_non_zero_gen:write_pointer_counter|auto_generated|safe_q[8] ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\write_address_non_zero_gen:write_pointer_counter|auto_generated|counter_cella8~COUT ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\write_address_non_zero_gen:write_pointer_counter|auto_generated|counter_cella8~COUTCOUT1_3 ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\write_address_non_zero_gen:write_pointer_counter|auto_generated|safe_q[9] ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\write_address_non_zero_gen:write_pointer_counter|auto_generated|counter_cella9~COUT ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\write_address_non_zero_gen:write_pointer_counter|auto_generated|counter_cella9~COUTCOUT1_3 ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\write_address_non_zero_gen:write_pointer_counter|auto_generated|safe_q[10] ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\write_address_non_zero_gen:write_pointer_counter|auto_generated|counter_cella10~COUT ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|\write_address_non_zero_gen:write_pointer_counter|auto_generated|cout ;
wire \auto_signaltap_0|sld_acquisition_buffer_inst|is_buffer_wrapped_once ;
wire \auto_signaltap_0|ela_control|sm1|post_trigger_count_enable~112 ;
wire \auto_signaltap_0|ela_control|sm1|post_trigger_count_enable ;
wire \auto_signaltap_0|ela_control|trigger_config_deserialize|dffs[6] ;
wire \auto_signaltap_0|ela_control|sm2|status_out~110 ;
wire \auto_signaltap_0|ela_control|sm2|status_out[0] ;
wire \auto_signaltap_0|ela_control|trigger_config_deserialize|dffs[5] ;
wire \sld_hub_inst|IRSR_D[2]~407 ;
wire \sld_hub_inst|IRSR_D[2]~406 ;
wire \sld_hub_inst|IRSR|Q[2] ;
wire \sld_hub_inst|instruction_decoder|auto_generated|dffe1a[7] ;
wire \sld_hub_inst|RESET|Q[0] ;
wire \auto_signaltap_0|ela_control|ela_status~77 ;
wire \sld_hub_inst|IRSR|Q[0] ;
wire \sld_hub_inst|\GEN_SHADOW_IRF:1:S_IRF|Q[0] ;
wire \sld_hub_inst|\GEN_IRF:1:IRF|Q[0] ;
wire \auto_signaltap_0|reset_all ;
wire \auto_signaltap_0|ela_control|\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|trigger_condition_deserialize|dffs[17] ;
wire \auto_signaltap_0|ela_control|\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|trigger_condition_deserialize|dffs[16] ;
wire \auto_signaltap_0|ela_control|\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|trigger_condition_deserialize|dffs[15] ;
wire \auto_signaltap_0|ela_control|\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|trigger_condition_deserialize|dffs[14] ;
wire \auto_signaltap_0|ela_control|\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|trigger_condition_deserialize|dffs[13] ;
wire \auto_signaltap_0|ela_control|\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|\trigger_modules_gen:0:trigger_match|\gen_sbpmg_pipeline_less_than_two:sm0:4:sm1|p_match_out~206 ;
wire \auto_signaltap_0|ela_control|\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|\trigger_modules_gen:0:trigger_match|\gen_sbpmg_pipeline_less_than_two:sm0:4:sm1|holdff ;
wire \auto_signaltap_0|ela_control|\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|\trigger_modules_gen:0:trigger_match|\gen_sbpmg_pipeline_less_than_two:sm0:4:sm1|match_out ;
wire \auto_signaltap_0|ela_control|\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|\trigger_modules_gen:0:trigger_match|\gen_sbpmg_pipeline_less_than_two:sm0:2:sm1|holdff ;
wire \auto_signaltap_0|ela_control|\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|\trigger_modules_gen:0:trigger_match|\gen_sbpmg_pipeline_less_than_two:sm0:2:sm1|p_match_out~206 ;
wire \auto_signaltap_0|ela_control|\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|\trigger_modules_gen:0:trigger_match|\gen_sbpmg_pipeline_less_than_two:sm0:2:sm1|match_out ;
wire \auto_signaltap_0|acq_trigger_in_reg[5] ;
wire \auto_signaltap_0|ela_control|\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|\trigger_modules_gen:0:trigger_match|\gen_sbpmg_pipeline_less_than_two:sm0:5:sm1|holdff ;
wire \auto_signaltap_0|ela_control|\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|\trigger_modules_gen:0:trigger_match|\gen_sbpmg_pipeline_less_than_two:sm0:5:sm1|p_match_out~209 ;
wire \auto_signaltap_0|ela_control|\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|\trigger_modules_gen:0:trigger_match|\gen_sbpmg_pipeline_less_than_two:sm0:5:sm1|match_out ;
wire \auto_signaltap_0|ela_control|\trigger_in_trigger_module_enabled_gen:trigger_in_match|\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1|p_match_out~206 ;
wire \auto_signaltap_0|trigger_in_reg ;
wire \auto_signaltap_0|ela_control|\trigger_in_trigger_module_enabled_gen:trigger_in_match|\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1|holdff ;
wire \auto_signaltap_0|ela_control|\trigger_in_trigger_module_enabled_gen:trigger_in_match|\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1|match_out ;
wire \auto_signaltap_0|ela_control|ela_level_seq_mgr|process0~19 ;
wire \auto_signaltap_0|ela_control|ela_level_seq_mgr|trigger_happened_ff[0] ;
wire \auto_signaltap_0|ela_control|\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|\trigger_modules_gen:0:trigger_match|\gen_sbpmg_pipeline_less_than_two:sm0:1:sm1|p_match_out~206 ;
wire \auto_signaltap_0|ela_control|\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|\trigger_modules_gen:0:trigger_match|\gen_sbpmg_pipeline_less_than_two:sm0:1:sm1|holdff ;
wire \auto_signaltap_0|ela_control|\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|\trigger_modules_gen:0:trigger_match|\gen_sbpmg_pipeline_less_than_two:sm0:1:sm1|match_out ;
wire \auto_signaltap_0|ela_control|\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|\trigger_modules_gen:0:trigger_match|\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1|holdff ;
wire \auto_signaltap_0|ela_control|\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|\trigger_modules_gen:0:trigger_match|\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1|p_match_out~206 ;
wire \auto_signaltap_0|ela_control|\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|\trigger_modules_gen:0:trigger_match|\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1|match_out ;
wire \auto_signaltap_0|ela_control|ela_level_seq_mgr|trigger_happened~115 ;