colorbar.vo

我买的红色飓风FPGA,EP1C6开发板的配套USBA实验例程 VGA模块的程序

// Copyright (C) 1991-2005 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic       
// functions, and any output files any of the foregoing           
// (including device programming or simulation files), and any    
// associated documentation or information are expressly subject  
// to the terms and conditions of the Altera Program License      
// Subscription Agreement, Altera MegaCore Function License       
// Agreement, or other applicable license agreement, including,   
// without limitation, that your use is for the sole purpose of   
// programming logic devices manufactured by Altera and sold by   
// Altera or its authorized distributors.  Please refer to the    
// applicable agreement for further details.

// VENDOR "Altera"
// PROGRAM "Quartus II"
// VERSION "Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version"

// DATE "02/23/2006 10:13:37"

// 
// Device: Altera EP1C6Q240C8 Package PQFP240
// 

// 
// This Verilog file should be used for ModelSim (Verilog) only
// 

`timescale 1 ps/ 1 ps

module 	ColorBar (
	rst,
	altera_reserved_tms,
	altera_reserved_tck,
	altera_reserved_tdi,
	clk,
	VGA_HS,
	VGA_VS,
	VGA_RGB,
	altera_reserved_tdo);
input 	rst;
input 	altera_reserved_tms;
input 	altera_reserved_tck;
input 	altera_reserved_tdi;
input 	clk;
output 	VGA_HS;
output 	VGA_VS;
output 	[2:0] VGA_RGB;
output 	altera_reserved_tdo;

wire gnd = 1'b0;
wire vcc = 1'b1;

tri1 devclrn;
tri1 devpor;
tri0 devoe;
// synopsys translate_off
initial $sdf_annotate("ColorBar_v.sdo");
// synopsys translate_on

wire \inst4|altpll_component|_clk1 ;
wire \inst4|altpll_component|_clk2 ;
wire \inst4|altpll_component|_clk3 ;
wire \inst4|altpll_component|_clk4 ;
wire \inst4|altpll_component|_clk5 ;
wire \auto_signaltap_0|bypass_reg_out ;
wire \auto_signaltap_0|ela_control|trigger_config_deserialize|dffs[0] ;
wire \sld_hub_inst|HUB_BYPASS_REG ;
wire \auto_signaltap_0|ela_control|sm2|status_out[2] ;
wire \clk~combout ;
wire \inst4|altpll_component|_clk0 ;
wire \rst~combout ;
wire \inst|hcnt[0] ;
wire \inst|hcnt[0]~430 ;
wire \inst|hcnt[0]~430COUT1_447 ;
wire \inst|hcnt[1] ;
wire \inst|hcnt[1]~434 ;
wire \inst|hcnt[1]~434COUT1_449 ;
wire \inst|hcnt[2] ;
wire \inst|hcnt[2]~406 ;
wire \inst|hcnt[2]~406COUT1_451 ;
wire \inst|hcnt[3] ;
wire \inst|hcnt[3]~398 ;
wire \inst|hcnt[3]~398COUT1_453 ;
wire \inst|hcnt[4] ;
wire \inst|hcnt[4]~394 ;
wire \inst|hcnt[5] ;
wire \inst|hcnt[5]~402 ;
wire \inst|hcnt[5]~402COUT1_455 ;
wire \inst|hcnt[6] ;
wire \inst|LessThan~1874 ;
wire \inst|hcnt[6]~410 ;
wire \inst|hcnt[6]~410COUT1_457 ;
wire \inst|hcnt[7]~414 ;
wire \inst|hcnt[7]~414COUT1_459 ;
wire \inst|hcnt[8] ;
wire \inst|hcnt[8]~418 ;
wire \inst|hcnt[8]~418COUT1_461 ;
wire \inst|hcnt[9] ;
wire \inst|hcnt[9]~422 ;
wire \inst|hcnt[10] ;
wire \inst|LessThan~1887 ;
wire \inst|hcnt[7] ;
wire \inst|pixel[0]~1416 ;
wire \inst|LessThan~1880 ;
wire \inst|LessThan~1884 ;
wire \inst|LessThan~1885 ;
wire \inst|hsyncint ;
wire \inst|vcnt[0] ;
wire \inst|vcnt[0]~237 ;
wire \inst|vcnt[0]~237COUT1_286 ;
wire \inst|vcnt[1] ;
wire \inst|vcnt[1]~241 ;
wire \inst|vcnt[1]~241COUT1_288 ;
wire \inst|vcnt[2] ;
wire \inst|vcnt[2]~245 ;
wire \inst|vcnt[2]~245COUT1_290 ;
wire \inst|vcnt[3] ;
wire \inst|vcnt[3]~253 ;
wire \inst|vcnt[3]~253COUT1_292 ;
wire \inst|vcnt[4] ;
wire \inst|vcnt[4]~257 ;
wire \inst|vcnt[5] ;
wire \inst|vcnt[5]~233 ;
wire \inst|vcnt[5]~233COUT1_294 ;
wire \inst|vcnt[6] ;
wire \inst|vcnt[6]~261 ;
wire \inst|vcnt[6]~261COUT1_296 ;
wire \inst|vcnt[7]~269 ;
wire \inst|vcnt[7]~269COUT1_298 ;
wire \inst|vcnt[8] ;
wire \inst|always4~157 ;
wire \inst|vcnt[8]~273 ;
wire \inst|vcnt[8]~273COUT1_300 ;
wire \inst|vcnt[9] ;
wire \inst|vcnt[9]~249 ;
wire \inst|vcnt[10] ;
wire \inst|always4~156 ;
wire \inst|LessThan~1888 ;
wire \inst|LessThan~1889 ;
wire \inst|vcnt[7] ;
wire \inst|LessThan~1886 ;
wire \inst|always4~155 ;
wire \inst|always3~127 ;
wire \inst|vsync ;
wire \inst|LessThan~1881 ;
wire \inst|pixel~1404 ;
wire \inst|pixel~1405 ;
wire \inst|pixel[2]~1406 ;
wire \inst|LessThan~1873 ;
wire \inst|LessThan~1877 ;
wire \inst|LessThan~1878 ;
wire \inst|LessThan~1879 ;
wire \inst|LessThan~1875 ;
wire \inst|LessThan~1876 ;
wire \inst|always4~160 ;
wire \inst|always4~161 ;
wire \inst|always4~158 ;
wire \inst|always4~159 ;
wire \inst|enable ;
wire \inst|pixel[2]~1407 ;
wire \inst|pixel[2]~1408 ;
wire \inst|pixel[2]~1409 ;
wire \inst|LessThan~1882 ;
wire \inst|pixel[1]~1410 ;
wire \inst|pixel[1]~1411 ;
wire \inst|pixel[1]~1412 ;
wire \inst|pixel[1]~1413 ;
wire \inst|pixel[0]~1417 ;
wire \inst|pixel[0]~1418 ;
wire \inst|pixel[0]~1419 ;
wire \inst|LessThan~1883 ;
wire \inst|pixel[0]~1414 ;
wire \inst|pixel[0]~1421 ;
wire \inst|pixel[0]~1415 ;
wire \inst|pixel[0]~1420 ;
wire \altera_reserved_tms~combout ;
wire \altera_reserved_tck~combout ;
wire \altera_reserved_tdi~combout ;
wire \altera_internal_jtag~TMSUTAP ;
wire \sld_hub_inst|jtag_state_machine|state[9] ;
wire \sld_hub_inst|jtag_state_machine|state[10] ;
wire \sld_hub_inst|jtag_state_machine|state[11] ;
wire \sld_hub_inst|jtag_state_machine|state[12] ;
wire \sld_hub_inst|jtag_state_machine|state[13] ;
wire \sld_hub_inst|jtag_state_machine|state[14] ;
wire \sld_hub_inst|jtag_state_machine|state[15] ;
wire \sld_hub_inst|jtag_state_machine|state[5] ;
wire \sld_hub_inst|jtag_state_machine|state[6] ;
wire \sld_hub_inst|jtag_state_machine|state[7] ;
wire \sld_hub_inst|jtag_state_machine|state[8] ;
wire \sld_hub_inst|jtag_state_machine|tms_cnt[0] ;
wire \sld_hub_inst|jtag_state_machine|tms_cnt[1] ;
wire \sld_hub_inst|jtag_state_machine|tms_cnt[2] ;
wire \sld_hub_inst|jtag_state_machine|state~203 ;
wire \sld_hub_inst|jtag_state_machine|state[0] ;
wire \sld_hub_inst|jtag_state_machine|state[1] ;
wire \sld_hub_inst|jtag_state_machine|state[2] ;
wire \sld_hub_inst|jtag_state_machine|state[3] ;
wire \sld_hub_inst|jtag_state_machine|state[4] ;
wire altera_internal_jtag;
wire \sld_hub_inst|jtag_ir_register|dffs[9] ;
wire \sld_hub_inst|jtag_ir_register|dffs[8] ;
wire \sld_hub_inst|jtag_ir_register|dffs[7] ;
wire \sld_hub_inst|jtag_ir_register|dffs[6] ;
wire \sld_hub_inst|jtag_ir_register|dffs[5] ;
wire \sld_hub_inst|jtag_ir_register|dffs[4] ;
wire \sld_hub_inst|jtag_ir_register|dffs[3] ;
wire \sld_hub_inst|jtag_ir_register|dffs[2] ;
wire \sld_hub_inst|reduce_nor~57 ;
wire \sld_hub_inst|jtag_ir_register|dffs[1] ;
wire \sld_hub_inst|reduce_nor~56 ;
wire \sld_hub_inst|jtag_ir_register|dffs[0] ;
wire \sld_hub_inst|jtag_debug_mode_usr1 ;