📄 colorbar_v.sdo

📁 我买的红色飓风FPGA,EP1C6开发板的配套USBA实验例程 VGA模块的程序
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    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (SETUP sclr (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
      (HOLD sclr (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE inst\|hcnt\[9\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (502:502:502) (512:512:512))
        (IOPATH datab regin (607:607:607) (607:607:607))
        (IOPATH cin regin (898:898:898) (898:898:898))
        (IOPATH cin0 regin (783:783:783) (783:783:783))
        (IOPATH cin1 regin (787:787:787) (787:787:787))
        (IOPATH datab cout (583:583:583) (583:583:583))
        (IOPATH cin cout (136:136:136) (136:136:136))
        (IOPATH cin0 cout (178:178:178) (178:178:178))
        (IOPATH cin1 cout (157:157:157) (157:157:157))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE inst\|hcnt\[9\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT sclr (1793:1793:1793) (1846:1846:1846))
        (PORT aclr (1418:1418:1418) (1397:1397:1397))
        (PORT clk (2397:2397:2397) (2376:2376:2376))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (SETUP sclr (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
      (HOLD sclr (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE inst\|hcnt\[10\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datad (555:555:555) (551:551:551))
        (IOPATH datad regin (309:309:309) (309:309:309))
        (IOPATH cin regin (839:839:839) (839:839:839))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE inst\|hcnt\[10\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT sclr (1793:1793:1793) (1846:1846:1846))
        (PORT aclr (1418:1418:1418) (1397:1397:1397))
        (PORT clk (2397:2397:2397) (2376:2376:2376))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (SETUP sclr (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
      (HOLD sclr (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE inst\|LessThan\~1887_I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (773:773:773) (760:760:760))
        (PORT datab (881:881:881) (844:844:844))
        (PORT datac (864:864:864) (854:854:854))
        (PORT datad (984:984:984) (922:922:922))
        (IOPATH dataa combout (590:590:590) (590:590:590))
        (IOPATH datab combout (442:442:442) (442:442:442))
        (IOPATH datac combout (292:292:292) (292:292:292))
        (IOPATH datad combout (114:114:114) (114:114:114))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE inst\|pixel\[0\]\~1416_I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datac (523:523:523) (553:553:553))
        (PORT datad (556:556:556) (553:553:553))
        (IOPATH datac combout (292:292:292) (292:292:292))
        (IOPATH datad combout (114:114:114) (114:114:114))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE inst\|LessThan\~1880_I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (520:520:520) (527:527:527))
        (PORT datac (586:586:586) (596:596:596))
        (PORT datad (1475:1475:1475) (1480:1480:1480))
        (IOPATH datab combout (442:442:442) (442:442:442))
        (IOPATH datac combout (292:292:292) (292:292:292))
        (IOPATH datad combout (114:114:114) (114:114:114))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE inst\|LessThan\~1884_I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (1479:1479:1479) (1489:1489:1489))
        (PORT datab (503:503:503) (516:516:516))
        (PORT datac (585:585:585) (595:595:595))
        (PORT datad (547:547:547) (545:545:545))
        (IOPATH dataa combout (590:590:590) (590:590:590))
        (IOPATH datab combout (442:442:442) (442:442:442))
        (IOPATH datac combout (292:292:292) (292:292:292))
        (IOPATH datad combout (114:114:114) (114:114:114))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE inst\|LessThan\~1885_I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (458:458:458) (460:460:460))
        (PORT datab (1282:1282:1282) (1293:1293:1293))
        (PORT datac (578:578:578) (589:589:589))
        (PORT datad (182:182:182) (182:182:182))
        (IOPATH dataa combout (590:590:590) (590:590:590))
        (IOPATH datab combout (442:442:442) (442:442:442))
        (IOPATH datac combout (292:292:292) (292:292:292))
        (IOPATH datad combout (114:114:114) (114:114:114))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE inst\|hsyncint\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (1529:1529:1529) (1552:1552:1552))
        (PORT datab (1409:1409:1409) (1438:1438:1438))
        (PORT datac (1555:1555:1555) (1580:1580:1580))
        (PORT datad (1867:1867:1867) (1902:1902:1902))
        (IOPATH dataa regin (738:738:738) (738:738:738))
        (IOPATH datab regin (607:607:607) (607:607:607))
        (IOPATH datac regin (478:478:478) (478:478:478))
        (IOPATH datad regin (309:309:309) (309:309:309))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE inst\|hsyncint\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (1418:1418:1418) (1397:1397:1397))
        (PORT clk (2397:2397:2397) (2376:2376:2376))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE inst\|vcnt\[0\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (508:508:508) (513:513:513))
        (IOPATH datab regin (607:607:607) (607:607:607))
        (IOPATH datab cout0 (423:423:423) (423:423:423))
        (IOPATH datab cout1 (432:432:432) (432:432:432))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE inst\|vcnt\[0\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT sclr (2283:2283:2283) (2377:2377:2377))
        (PORT aclr (1418:1418:1418) (1397:1397:1397))
        (PORT clk (4732:4732:4732) (4781:4781:4781))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (SETUP sclr (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
      (HOLD sclr (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE inst\|vcnt\[1\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (532:532:532) (540:540:540))
        (IOPATH dataa regin (738:738:738) (738:738:738))
        (IOPATH cin0 regin (783:783:783) (783:783:783))
        (IOPATH cin1 regin (787:787:787) (787:787:787))
        (IOPATH dataa cout0 (564:564:564) (564:564:564))
        (IOPATH cin0 cout0 (78:78:78) (78:78:78))
        (IOPATH dataa cout1 (575:575:575) (575:575:575))
        (IOPATH cin1 cout1 (80:80:80) (80:80:80))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE inst\|vcnt\[1\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT sclr (2283:2283:2283) (2377:2377:2377))
        (PORT aclr (1418:1418:1418) (1397:1397:1397))
        (PORT clk (4732:4732:4732) (4781:4781:4781))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (SETUP sclr (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
      (HOLD sclr (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE inst\|vcnt\[2\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (530:530:530) (540:540:540))
        (IOPATH dataa regin (738:738:738) (738:738:738))
        (IOPATH cin0 regin (783:783:783) (783:783:783))
        (IOPATH cin1 regin (787:787:787) (787:787:787))
        (IOPATH dataa cout0 (564:564:564) (564:564:564))
        (IOPATH cin0 cout0 (78:78:78) (78:78:78))
        (IOPATH dataa cout1 (575:575:575) (575:575:575))
        (IOPATH cin1 cout1 (80:80:80) (80:80:80))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE inst\|vcnt\[2\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT sclr (2283:2283:2283) (2377:2377:2377))
        (PORT aclr (1418:1418:1418) (1397:1397:1397))
        (PORT clk (4732:4732:4732) (4781:4781:4781))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (SETUP sclr (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
      (HOLD sclr (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE inst\|vcnt\[3\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (492:492:492) (506:506:506))
        (IOPATH datab regin (607:607:607) (607:607:607))
        (IOPATH cin0 regin (783:783:783) (783:783:783))
        (IOPATH cin1 regin (787:787:787) (787:787:787))
        (IOPATH datab cout0 (423:423:423) (423:423:423))
        (IOPATH cin0 cout0 (78:78:78) (78:78:78))
        (IOPATH datab cout1 (432:432:432) (432:432:432))
        (IOPATH cin1 cout1 (80:80:80) (80:80:80))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE inst\|vcnt\[3\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT sclr (2283:2283:2283) (2377:2377:2377))
        (PORT aclr (1418:1418:1418) (1397:1397:1397))
        (PORT clk (4732:4732:4732) (4781:4781:4781))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (SETUP sclr (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
      (HOLD sclr (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE inst\|vcnt\[4\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (520:520:520) (534:534:534))
        (IOPATH dataa regin (738:738:738) (738:738:738))
        (IOPATH cin0 regin (783:783:783) (783:783:783))
        (IOPATH cin1 regin (787:787:787) (787:787:787))
        (IOPATH dataa cout (838:838:838) (838:838:838))
        (IOPATH cin0 cout (271:271:271) (271:271:271))
        (IOPATH cin1 cout (258:258:258) (258:258:258))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE inst\|vcnt\[4\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT sclr (2283:2283:2283) (2377:2377:2377))
        (PORT aclr (1418:1418:1418) (1397:1397:1397))
        (PORT clk (4732:4732:4732) (4781:4781:4781))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (SETUP sclr (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
      (HOLD sclr (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE inst\|vcnt\[5\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (527:527:527) (529:529:529))
        (IOPATH datab regin (607:607:607) (607:607:607))
        (IOPATH cin regin (898:898:898) (898:898:898))
        (IOPATH datab cout0 (423:423:423) (423:423:423))
        (IOPATH datab cout1 (432:432:432) (432:432:432))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE inst\|vcnt\[5\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT sclr (1520:1520:1520) (1579:1579:1579))
        (PORT aclr (1418:1418:1418) (1397:1397:1397))
        (PORT clk (4732:4732:4732) (4781:4781:4781))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (SETUP sclr (posedge clk) (37:37:37))
💿 文件大小 3118 K
👤 上传用户 xufengping716
📂 所属分类 VHDL/FPGA/Verilog
🏷️ 相关标签

#FPGA #USBA #VGA #EP
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