colorbar_v.sdo

我买的红色飓风FPGA,EP1C6开发板的配套USBA实验例程 VGA模块的程序

// Copyright (C) 1991-2005 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic       
// functions, and any output files any of the foregoing           
// (including device programming or simulation files), and any    
// associated documentation or information are expressly subject  
// to the terms and conditions of the Altera Program License      
// Subscription Agreement, Altera MegaCore Function License       
// Agreement, or other applicable license agreement, including,   
// without limitation, that your use is for the sole purpose of   
// programming logic devices manufactured by Altera and sold by   
// Altera or its authorized distributors.  Please refer to the    
// applicable agreement for further details.


// 
// Device: Altera EP1C6Q240C8 Package PQFP240
// 

// 
// This SDF file should be used for ModelSim (Verilog) only
// 

(DELAYFILE
  (SDFVERSION "2.1")
  (DESIGN "ColorBar")
  (DATE "02/23/2006 10:13:37")
  (VENDOR "Altera")
  (PROGRAM "Quartus II")
  (VERSION "Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version")
  (DIVIDER .)
  (TIMESCALE 1 ps)

  (CELL
    (CELLTYPE "cyclone_asynch_io")
    (INSTANCE clk\~I.asynch_inst)
    (DELAY
      (ABSOLUTE
        (IOPATH padio combout (1469:1469:1469) (1469:1469:1469))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_pll")
    (INSTANCE inst4\|altpll_component\|pll)
    (DELAY
      (ABSOLUTE
        (PORT inclk[0] (1846:1846:1846) (1846:1846:1846))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_io")
    (INSTANCE rst\~I.asynch_inst)
    (DELAY
      (ABSOLUTE
        (IOPATH padio combout (1469:1469:1469) (1469:1469:1469))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE inst\|hcnt\[0\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (498:498:498) (509:509:509))
        (IOPATH datab regin (607:607:607) (607:607:607))
        (IOPATH datab cout0 (423:423:423) (423:423:423))
        (IOPATH datab cout1 (432:432:432) (432:432:432))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE inst\|hcnt\[0\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT sclr (2257:2257:2257) (2353:2353:2353))
        (PORT aclr (1418:1418:1418) (1397:1397:1397))
        (PORT clk (2397:2397:2397) (2376:2376:2376))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (SETUP sclr (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
      (HOLD sclr (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE inst\|hcnt\[1\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (545:545:545) (547:547:547))
        (IOPATH dataa regin (738:738:738) (738:738:738))
        (IOPATH cin0 regin (783:783:783) (783:783:783))
        (IOPATH cin1 regin (787:787:787) (787:787:787))
        (IOPATH dataa cout0 (564:564:564) (564:564:564))
        (IOPATH cin0 cout0 (78:78:78) (78:78:78))
        (IOPATH dataa cout1 (575:575:575) (575:575:575))
        (IOPATH cin1 cout1 (80:80:80) (80:80:80))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE inst\|hcnt\[1\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT sclr (2257:2257:2257) (2353:2353:2353))
        (PORT aclr (1418:1418:1418) (1397:1397:1397))
        (PORT clk (2397:2397:2397) (2376:2376:2376))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (SETUP sclr (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
      (HOLD sclr (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE inst\|hcnt\[2\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (575:575:575) (571:571:571))
        (IOPATH dataa regin (738:738:738) (738:738:738))
        (IOPATH cin0 regin (783:783:783) (783:783:783))
        (IOPATH cin1 regin (787:787:787) (787:787:787))
        (IOPATH dataa cout0 (564:564:564) (564:564:564))
        (IOPATH cin0 cout0 (78:78:78) (78:78:78))
        (IOPATH dataa cout1 (575:575:575) (575:575:575))
        (IOPATH cin1 cout1 (80:80:80) (80:80:80))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE inst\|hcnt\[2\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT sclr (2257:2257:2257) (2353:2353:2353))
        (PORT aclr (1418:1418:1418) (1397:1397:1397))
        (PORT clk (2397:2397:2397) (2376:2376:2376))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (SETUP sclr (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
      (HOLD sclr (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE inst\|hcnt\[3\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (518:518:518) (525:525:525))
        (IOPATH datab regin (607:607:607) (607:607:607))
        (IOPATH cin0 regin (783:783:783) (783:783:783))
        (IOPATH cin1 regin (787:787:787) (787:787:787))
        (IOPATH datab cout0 (423:423:423) (423:423:423))
        (IOPATH cin0 cout0 (78:78:78) (78:78:78))
        (IOPATH datab cout1 (432:432:432) (432:432:432))
        (IOPATH cin1 cout1 (80:80:80) (80:80:80))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE inst\|hcnt\[3\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT sclr (2257:2257:2257) (2353:2353:2353))
        (PORT aclr (1418:1418:1418) (1397:1397:1397))
        (PORT clk (2397:2397:2397) (2376:2376:2376))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (SETUP sclr (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
      (HOLD sclr (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE inst\|hcnt\[4\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (584:584:584) (577:577:577))
        (IOPATH dataa regin (738:738:738) (738:738:738))
        (IOPATH cin0 regin (783:783:783) (783:783:783))
        (IOPATH cin1 regin (787:787:787) (787:787:787))
        (IOPATH dataa cout (838:838:838) (838:838:838))
        (IOPATH cin0 cout (271:271:271) (271:271:271))
        (IOPATH cin1 cout (258:258:258) (258:258:258))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE inst\|hcnt\[4\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT sclr (2257:2257:2257) (2353:2353:2353))
        (PORT aclr (1418:1418:1418) (1397:1397:1397))
        (PORT clk (2397:2397:2397) (2376:2376:2376))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (SETUP sclr (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
      (HOLD sclr (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE inst\|hcnt\[5\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (534:534:534) (533:533:533))
        (IOPATH datab regin (607:607:607) (607:607:607))
        (IOPATH cin regin (898:898:898) (898:898:898))
        (IOPATH datab cout0 (423:423:423) (423:423:423))
        (IOPATH datab cout1 (432:432:432) (432:432:432))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE inst\|hcnt\[5\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT sclr (1793:1793:1793) (1846:1846:1846))
        (PORT aclr (1418:1418:1418) (1397:1397:1397))
        (PORT clk (2397:2397:2397) (2376:2376:2376))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (SETUP sclr (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
      (HOLD sclr (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE inst\|hcnt\[6\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (545:545:545) (547:547:547))
        (IOPATH dataa regin (738:738:738) (738:738:738))
        (IOPATH cin regin (898:898:898) (898:898:898))
        (IOPATH cin0 regin (783:783:783) (783:783:783))
        (IOPATH cin1 regin (787:787:787) (787:787:787))
        (IOPATH dataa cout0 (564:564:564) (564:564:564))
        (IOPATH cin0 cout0 (78:78:78) (78:78:78))
        (IOPATH dataa cout1 (575:575:575) (575:575:575))
        (IOPATH cin1 cout1 (80:80:80) (80:80:80))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE inst\|hcnt\[6\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT sclr (1793:1793:1793) (1846:1846:1846))
        (PORT aclr (1418:1418:1418) (1397:1397:1397))
        (PORT clk (2397:2397:2397) (2376:2376:2376))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (SETUP sclr (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
      (HOLD sclr (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE inst\|LessThan\~1874_I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (543:543:543) (544:544:544))
        (PORT datac (523:523:523) (552:552:552))
        (PORT datad (547:547:547) (545:545:545))
        (IOPATH datab combout (442:442:442) (442:442:442))
        (IOPATH datac combout (292:292:292) (292:292:292))
        (IOPATH datad combout (114:114:114) (114:114:114))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE inst\|hcnt\[7\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (522:522:522) (535:535:535))
        (IOPATH dataa regin (738:738:738) (738:738:738))
        (IOPATH cin regin (898:898:898) (898:898:898))
        (IOPATH cin0 regin (783:783:783) (783:783:783))
        (IOPATH cin1 regin (787:787:787) (787:787:787))
        (IOPATH dataa cout0 (564:564:564) (564:564:564))
        (IOPATH cin0 cout0 (78:78:78) (78:78:78))
        (IOPATH dataa cout1 (575:575:575) (575:575:575))
        (IOPATH cin1 cout1 (80:80:80) (80:80:80))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE inst\|hcnt\[7\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT sclr (1793:1793:1793) (1846:1846:1846))
        (PORT aclr (1418:1418:1418) (1397:1397:1397))
        (PORT clk (2397:2397:2397) (2376:2376:2376))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (SETUP sclr (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
      (HOLD sclr (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE inst\|hcnt\[8\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (522:522:522) (528:528:528))
        (IOPATH datab regin (607:607:607) (607:607:607))
        (IOPATH cin regin (898:898:898) (898:898:898))
        (IOPATH cin0 regin (783:783:783) (783:783:783))
        (IOPATH cin1 regin (787:787:787) (787:787:787))
        (IOPATH datab cout0 (423:423:423) (423:423:423))
        (IOPATH cin0 cout0 (78:78:78) (78:78:78))
        (IOPATH datab cout1 (432:432:432) (432:432:432))
        (IOPATH cin1 cout1 (80:80:80) (80:80:80))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE inst\|hcnt\[8\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT sclr (1793:1793:1793) (1846:1846:1846))
        (PORT aclr (1418:1418:1418) (1397:1397:1397))
        (PORT clk (2397:2397:2397) (2376:2376:2376))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )