_primary.vhd

来自「我买的红色飓风FPGA,EP1C6开发板的配套USBA实验例程 VGA模块的程序」· VHDL 代码 · 共 9 行

library verilog;
use verilog.vl_types.all;
entity cyclone_and16 is
    port(
        Y               : out    vl_logic_vector(15 downto 0);
        IN1             : in     vl_logic_vector(15 downto 0)
    );
end cyclone_and16;