lcd_v.tan.rpt

我买的红色飓风FPGA,EP1C6开发板的配套USBA实验例程 LCD模块的程序

+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                             ;
+---------------------------------------------+------------------------------------------+---------------+----------------------------------+----------------------------------------------------+-------------------------------------------------------+------------------------------+------------------------------+--------------+
; Type                                        ; Slack                                    ; Required Time ; Actual Time                      ; From                                               ; To                                                    ; From Clock                   ; To Clock                     ; Failed Paths ;
+---------------------------------------------+------------------------------------------+---------------+----------------------------------+----------------------------------------------------+-------------------------------------------------------+------------------------------+------------------------------+--------------+
; Worst-case tsu                              ; N/A                                      ; None          ; -0.256 ns                        ; altera_internal_jtag~TMSUTAP                       ; sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0|Q[0]         ;                              ; altera_internal_jtag~TCKUTAP ; 0            ;
; Worst-case tco                              ; N/A                                      ; None          ; 27.300 ns                        ; lcd:inst1|always4~0                                ; data[4]                                               ; mclk                         ;                              ; 0            ;
; Worst-case tpd                              ; N/A                                      ; None          ; 2.124 ns                         ; altera_internal_jtag~TDO                           ; altera_reserved_tdo                                   ;                              ;                              ; 0            ;
; Worst-case th                               ; N/A                                      ; None          ; 18.148 ns                        ; rst                                                ; lcd:inst1|lcd_rs                                      ;                              ; mclk                         ; 0            ;
; Clock Setup: 'mclk'                         ; N/A                                      ; None          ; 48.66 MHz ( period = 20.552 ns ) ; lcd:inst1|lcd_e                                    ; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[14] ; mclk                         ; mclk                         ; 0            ;
; Clock Setup: 'altera_internal_jtag~TCKUTAP' ; N/A                                      ; None          ; 100.52 MHz ( period = 9.948 ns ) ; sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[3] ; sld_hub:sld_hub_inst|hub_tdo                          ; altera_internal_jtag~TCKUTAP ; altera_internal_jtag~TCKUTAP ; 0            ;
; Clock Hold: 'mclk'                          ; Not operational: Clock Skew > Data Delay ; None          ; N/A                              ; lcd:inst1|state.SWITCHMODE                         ; lcd:inst1|state.CLEAR                                 ; mclk                         ; mclk                         ; 17           ;
; Total number of failed paths                ;                                          ;               ;                                  ;                                                    ;                                                       ;                              ;                              ; 17           ;
+---------------------------------------------+------------------------------------------+---------------+----------------------------------+----------------------------------------------------+-------------------------------------------------------+------------------------------+------------------------------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C6Q240C8        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;