lcd_v.fit.qmsg

我买的红色飓风FPGA,EP1C6开发板的配套USBA实验例程 LCD模块的程序

{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "0.805 ns register register " "Info: Estimated most critical path is register to register delay of 0.805 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lcd:inst1\|lcd_e 1 REG LAB_X13_Y14 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X13_Y14; Fanout = 3; REG Node = 'lcd:inst1\|lcd_e'" {  } { { "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/" "" "" { lcd:inst1|lcd_e } "NODE_NAME" } "" } } { "lcd.v" "" { Text "E:/code/EP1C6/S4_LCD_V/proj/lcd.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.690 ns) + CELL(0.115 ns) 0.805 ns sld_signaltap:auto_signaltap_0\|acq_trigger_in_reg\[14\] 2 REG LAB_X13_Y14 5 " "Info: 2: + IC(0.690 ns) + CELL(0.115 ns) = 0.805 ns; Loc. = LAB_X13_Y14; Fanout = 5; REG Node = 'sld_signaltap:auto_signaltap_0\|acq_trigger_in_reg\[14\]'" {  } { { "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/" "" "0.805 ns" { lcd:inst1|lcd_e sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[14] } "NODE_NAME" } "" } } { "sld_signaltap.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 437 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.115 ns 14.29 % " "Info: Total cell delay = 0.115 ns ( 14.29 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.690 ns 85.71 % " "Info: Total interconnect delay = 0.690 ns ( 85.71 % )" {  } {  } 0}  } { { "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/" "" "0.805 ns" { lcd:inst1|lcd_e sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[14] } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Info: Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "2 8 " "Info: Average interconnect usage is 2% of the available device resources. Peak interconnect usage is 8%." {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Info: Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements" {  } {  } 0}
{ "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE_TOP_MSG" "sld_signaltap:auto_signaltap_0\|reset_all " "Info: Node sld_signaltap:auto_signaltap_0\|reset_all uses non-global routing resources to route signals to global destination nodes" { { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_signaltap:auto_signaltap_0\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:ram_data_shift_out\|dffs\[1\] " "Info: Port clear -- assigned as a global for destination node sld_signaltap:auto_signaltap_0\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:ram_data_shift_out\|dffs\[1\] -- routed using non-global resources" {  } { { "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/" "" "" { sld_signaltap:auto_signaltap_0|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sld_signaltap:auto_signaltap_0\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:ram_data_shift_out\|dffs\[1\]" } } } } { "lpm_shiftreg.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_shiftreg.tdf" 54 7 0 } } { "E:/code/EP1C6/S4_LCD_V/proj/lcd_v.fld" "" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/lcd_v.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[1] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_signaltap:auto_signaltap_0\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:ram_data_shift_out\|dffs\[2\] " "Info: Port clear -- assigned as a global for destination node sld_signaltap:auto_signaltap_0\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:ram_data_shift_out\|dffs\[2\] -- routed using non-global resources" {  } { { "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/" "" "" { sld_signaltap:auto_signaltap_0|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[2] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sld_signaltap:auto_signaltap_0\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:ram_data_shift_out\|dffs\[2\]" } } } } { "lpm_shiftreg.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_shiftreg.tdf" 54 7 0 } } { "E:/code/EP1C6/S4_LCD_V/proj/lcd_v.fld" "" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/lcd_v.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[2] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_signaltap:auto_signaltap_0\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:ram_data_shift_out\|dffs\[0\] " "Info: Port clear -- assigned as a global for destination node sld_signaltap:auto_signaltap_0\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:ram_data_shift_out\|dffs\[0\] -- routed using non-global resources" {  } { { "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/" "" "" { sld_signaltap:auto_signaltap_0|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sld_signaltap:auto_signaltap_0\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:ram_data_shift_out\|dffs\[0\]" } } } } { "lpm_shiftreg.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_shiftreg.tdf" 54 7 0 } } { "E:/code/EP1C6/S4_LCD_V/proj/lcd_v.fld" "" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/lcd_v.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[0] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_counter:\\non_zero_sample_depth_gen:segment_addr_counter\|cntr_f29:auto_generated\|counter_cella5 " "Info: Port clear -- assigned as a global for destination node sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_counter:\\non_zero_sample_depth_gen:segment_addr_counter\|cntr_f29:auto_generated\|counter_cella5 -- routed using non-global resources" {  } { { "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/" "" "" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_f29:auto_generated|safe_q[5] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_counter:\\non_zero_sample_depth_gen:segment_addr_counter\|cntr_f29:auto_generated\|safe_q\[5\]" } } } } { "db/cntr_f29.tdf" "" { Text "E:/code/EP1C6/S4_LCD_V/proj/db/cntr_f29.tdf" 128 8 0 } } { "E:/code/EP1C6/S4_LCD_V/proj/lcd_v.fld" "" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/lcd_v.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_f29:auto_generated|safe_q[5] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_counter:\\non_zero_sample_depth_gen:segment_addr_counter\|cntr_f29:auto_generated\|counter_cella6 " "Info: Port clear -- assigned as a global for destination node sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_counter:\\non_zero_sample_depth_gen:segment_addr_counter\|cntr_f29:auto_generated\|counter_cella6 -- routed using non-global resources" {  } { { "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/" "" "" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_f29:auto_generated|safe_q[6] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_counter:\\non_zero_sample_depth_gen:segment_addr_counter\|cntr_f29:auto_generated\|safe_q\[6\]" } } } } { "db/cntr_f29.tdf" "" { Text "E:/code/EP1C6/S4_LCD_V/proj/db/cntr_f29.tdf" 128 8 0 } } { "E:/code/EP1C6/S4_LCD_V/proj/lcd_v.fld" "" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/lcd_v.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_f29:auto_generated|safe_q[6] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_counter:\\non_zero_sample_depth_gen:segment_addr_counter\|cntr_f29:auto_generated\|counter_cella7 " "Info: Port clear -- assigned as a global for destination node sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_counter:\\non_zero_sample_depth_gen:segment_addr_counter\|cntr_f29:auto_generated\|counter_cella7 -- routed using non-global resources" {  } { { "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/" "" "" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_f29:auto_generated|safe_q[7] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_counter:\\non_zero_sample_depth_gen:segment_addr_counter\|cntr_f29:auto_generated\|safe_q\[7\]" } } } } { "db/cntr_f29.tdf" "" { Text "E:/code/EP1C6/S4_LCD_V/proj/db/cntr_f29.tdf" 128 8 0 } } { "E:/code/EP1C6/S4_LCD_V/proj/lcd_v.fld" "" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/lcd_v.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_f29:auto_generated|safe_q[7] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_counter:\\non_zero_sample_depth_gen:segment_addr_counter\|cntr_f29:auto_generated\|counter_cella8 " "Info: Port clear -- assigned as a global for destination node sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_counter:\\non_zero_sample_depth_gen:segment_addr_counter\|cntr_f29:auto_generated\|counter_cella8 -- routed using non-global resources" {  } { { "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/" "" "" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_f29:auto_generated|safe_q[8] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_counter:\\non_zero_sample_depth_gen:segment_addr_counter\|cntr_f29:auto_generated\|safe_q\[8\]" } } } } { "db/cntr_f29.tdf" "" { Text "E:/code/EP1C6/S4_LCD_V/proj/db/cntr_f29.tdf" 128 8 0 } } { "E:/code/EP1C6/S4_LCD_V/proj/lcd_v.fld" "" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/lcd_v.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_f29:auto_generated|safe_q[8] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_counter:\\non_zero_sample_depth_gen:segment_addr_counter\|cntr_f29:auto_generated\|counter_cella9 " "Info: Port clear -- assigned as a global for destination node sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_counter:\\non_zero_sample_depth_gen:segment_addr_counter\|cntr_f29:auto_generated\|counter_cella9 -- routed using non-global resources" {  } { { "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/" "" "" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_f29:auto_generated|safe_q[9] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_counter:\\non_zero_sample_depth_gen:segment_addr_counter\|cntr_f29:auto_generated\|safe_q\[9\]" } } } } { "db/cntr_f29.tdf" "" { Text "E:/code/EP1C6/S4_LCD_V/proj/db/cntr_f29.tdf" 128 8 0 } } { "E:/code/EP1C6/S4_LCD_V/proj/lcd_v.fld" "" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/lcd_v.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_f29:auto_generated|safe_q[9] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_counter:\\non_zero_sample_depth_gen:segment_addr_counter\|cntr_f29:auto_generated\|counter_cella10 " "Info: Port clear -- assigned as a global for destination node sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_counter:\\non_zero_sample_depth_gen:segment_addr_counter\|cntr_f29:auto_generated\|counter_cella10 -- routed using non-global resources" {  } { { "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/" "" "" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_f29:auto_generated|safe_q[10] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_counter:\\non_zero_sample_depth_gen:segment_addr_counter\|cntr_f29:auto_generated\|safe_q\[10\]" } } } } { "db/cntr_f29.tdf" "" { Text "E:/code/EP1C6/S4_LCD_V/proj/db/cntr_f29.tdf" 128 8 0 } } { "E:/code/EP1C6/S4_LCD_V/proj/lcd_v.fld" "" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/lcd_v.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_f29:auto_generated|safe_q[10] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|segment_write_addr_adv_ena " "Info: Port clear -- assigned as a global for destination node sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|segment_write_addr_adv_ena -- routed using non-global resources" {  } { { "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/" "" "" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|segment_write_addr_adv_ena" } } } } { "sld_ela_control.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_ela_control.vhd" 1399 -1 0 } } { "E:/code/EP1C6/S4_LCD_V/proj/lcd_v.fld" "" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/lcd_v.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena } "NODE_NAME" } }  } 0}  } { { "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/" "" "" { sld_signaltap:auto_signaltap_0|reset_all } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sld_signaltap:auto_signaltap_0\|reset_all" } } } } { "sld_signaltap.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 415 -1 0 } } { "E:/code/EP1C6/S4_LCD_V/proj/lcd_v.fld" "" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/lcd_v.fld" "" "" { sld_signaltap:auto_signaltap_0|reset_all } "NODE_NAME" } }  } 0}
{ "Warning" "WFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "1 " "Warning: The following 1 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "lcd_rw GND " "Info: Pin lcd_rw has GND driving its datain port" {  } { { "lcd_v.bdf" "" { Schematic "E:/code/EP1C6/S4_LCD_V/proj/lcd_v.bdf" { { 144 432 608 160 "lcd_rw" "" } } } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd_rw" } } } } { "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/" "" "" { lcd_rw } "NODE_NAME" } "" } } { "E:/code/EP1C6/S4_LCD_V/proj/lcd_v.fld" "" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/lcd_v.fld" "" "" { lcd_rw } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 20 21:14:48 2008 " "Info: Processing ended: Sun Apr 20 21:14:48 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:15 " "Info: Elapsed time: 00:00:15" {  } {  } 0}  } {  } 0}