lcd_v.tan.qmsg

我买的红色飓风FPGA,EP1C6开发板的配套USBA实验例程 LCD模块的程序

{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "lcd:inst1\|state.SWITCHMODE lcd:inst1\|state.CLEAR mclk 478 ps " "Info: Found hold time violation between source  pin or register \"lcd:inst1\|state.SWITCHMODE\" and destination pin or register \"lcd:inst1\|state.CLEAR\" for clock \"mclk\" (Hold time is 478 ps)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "1.345 ns + Largest " "Info: + Largest clock skew is 1.345 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "mclk destination 21.529 ns + Longest register " "Info: + Longest clock path from clock \"mclk\" to destination register is 21.529 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns mclk 1 CLK PIN_153 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 4; CLK Node = 'mclk'" {  } { { "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/" "" "" { mclk } "NODE_NAME" } "" } } { "lcd_v.bdf" "" { Schematic "E:/code/EP1C6/S4_LCD_V/proj/lcd_v.bdf" { { 48 -96 72 64 "mclk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.746 ns) + CELL(0.935 ns) 3.150 ns div16:inst\|count\[3\] 2 REG LC_X8_Y10_N2 270 " "Info: 2: + IC(0.746 ns) + CELL(0.935 ns) = 3.150 ns; Loc. = LC_X8_Y10_N2; Fanout = 270; REG Node = 'div16:inst\|count\[3\]'" {  } { { "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/" "" "1.681 ns" { mclk div16:inst|count[3] } "NODE_NAME" } "" } } { "DIV16.v" "" { Text "E:/code/EP1C6/S4_LCD_V/proj/DIV16.v" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.515 ns) + CELL(0.935 ns) 7.600 ns lcd:inst1\|clkcnt\[11\] 3 REG LC_X9_Y10_N3 4 " "Info: 3: + IC(3.515 ns) + CELL(0.935 ns) = 7.600 ns; Loc. = LC_X9_Y10_N3; Fanout = 4; REG Node = 'lcd:inst1\|clkcnt\[11\]'" {  } { { "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/" "" "4.450 ns" { div16:inst|count[3] lcd:inst1|clkcnt[11] } "NODE_NAME" } "" } } { "lcd.v" "" { Text "E:/code/EP1C6/S4_LCD_V/proj/lcd.v" 68 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.524 ns) + CELL(0.590 ns) 9.714 ns lcd:inst1\|reduce_nor~129 4 COMB LC_X8_Y11_N5 1 " "Info: 4: + IC(1.524 ns) + CELL(0.590 ns) = 9.714 ns; Loc. = LC_X8_Y11_N5; Fanout = 1; COMB Node = 'lcd:inst1\|reduce_nor~129'" {  } { { "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/" "" "2.114 ns" { lcd:inst1|clkcnt[11] lcd:inst1|reduce_nor~129 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.399 ns) + CELL(0.442 ns) 10.555 ns lcd:inst1\|reduce_nor~131 5 COMB LC_X8_Y11_N9 2 " "Info: 5: + IC(0.399 ns) + CELL(0.442 ns) = 10.555 ns; Loc. = LC_X8_Y11_N9; Fanout = 2; COMB Node = 'lcd:inst1\|reduce_nor~131'" {  } { { "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/" "" "0.841 ns" { lcd:inst1|reduce_nor~129 lcd:inst1|reduce_nor~131 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.480 ns) + CELL(0.935 ns) 11.970 ns lcd:inst1\|clkdiv 6 REG LC_X8_Y11_N6 3 " "Info: 6: + IC(0.480 ns) + CELL(0.935 ns) = 11.970 ns; Loc. = LC_X8_Y11_N6; Fanout = 3; REG Node = 'lcd:inst1\|clkdiv'" {  } { { "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/" "" "1.415 ns" { lcd:inst1|reduce_nor~131 lcd:inst1|clkdiv } "NODE_NAME" } "" } } { "lcd.v" "" { Text "E:/code/EP1C6/S4_LCD_V/proj/lcd.v" 84 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.035 ns) + CELL(0.935 ns) 16.940 ns lcd:inst1\|clk_int 7 REG LC_X10_Y10_N2 24 " "Info: 7: + IC(4.035 ns) + CELL(0.935 ns) = 16.940 ns; Loc. = LC_X10_Y10_N2; Fanout = 24; REG Node = 'lcd:inst1\|clk_int'" {  } { { "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/" "" "4.970 ns" { lcd:inst1|clkdiv lcd:inst1|clk_int } "NODE_NAME" } "" } } { "lcd.v" "" { Text "E:/code/EP1C6/S4_LCD_V/proj/lcd.v" 91 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.878 ns) + CELL(0.711 ns) 21.529 ns lcd:inst1\|state.CLEAR 8 REG LC_X9_Y9_N8 2 " "Info: 8: + IC(3.878 ns) + CELL(0.711 ns) = 21.529 ns; Loc. = LC_X9_Y9_N8; Fanout = 2; REG Node = 'lcd:inst1\|state.CLEAR'" {  } { { "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/" "" "4.589 ns" { lcd:inst1|clk_int lcd:inst1|state.CLEAR } "NODE_NAME" } "" } } { "lcd.v" "" { Text "E:/code/EP1C6/S4_LCD_V/proj/lcd.v" 8 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.952 ns 32.29 % " "Info: Total cell delay = 6.952 ns ( 32.29 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "14.577 ns 67.71 % " "Info: Total interconnect delay = 14.577 ns ( 67.71 % )" {  } {  } 0}  } { { "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/" "" "21.529 ns" { mclk div16:inst|count[3] lcd:inst1|clkcnt[11] lcd:inst1|reduce_nor~129 lcd:inst1|reduce_nor~131 lcd:inst1|clkdiv lcd:inst1|clk_int lcd:inst1|state.CLEAR } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "21.529 ns" { mclk mclk~out0 div16:inst|count[3] lcd:inst1|clkcnt[11] lcd:inst1|reduce_nor~129 lcd:inst1|reduce_nor~131 lcd:inst1|clkdiv lcd:inst1|clk_int lcd:inst1|state.CLEAR } { 0.0ns 0.0ns 0.746ns 3.515ns 1.524ns 0.399ns 0.48ns 4.035ns 3.878ns } { 0.0ns 1.469ns 0.935ns 0.935ns 0.59ns 0.442ns 0.935ns 0.935ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "mclk source 20.184 ns - Shortest register " "Info: - Shortest clock path from clock \"mclk\" to source register is 20.184 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns mclk 1 CLK PIN_153 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 4; CLK Node = 'mclk'" {  } { { "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/" "" "" { mclk } "NODE_NAME" } "" } } { "lcd_v.bdf" "" { Schematic "E:/code/EP1C6/S4_LCD_V/proj/lcd_v.bdf" { { 48 -96 72 64 "mclk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.746 ns) + CELL(0.935 ns) 3.150 ns div16:inst\|count\[3\] 2 REG LC_X8_Y10_N2 270 " "Info: 2: + IC(0.746 ns) + CELL(0.935 ns) = 3.150 ns; Loc. = LC_X8_Y10_N2; Fanout = 270; REG Node = 'div16:inst\|count\[3\]'" {  } { { "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/" "" "1.681 ns" { mclk div16:inst|count[3] } "NODE_NAME" } "" } } { "DIV16.v" "" { Text "E:/code/EP1C6/S4_LCD_V/proj/DIV16.v" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.517 ns) + CELL(0.935 ns) 7.602 ns lcd:inst1\|clkcnt\[1\] 3 REG LC_X9_Y11_N3 4 " "Info: 3: + IC(3.517 ns) + CELL(0.935 ns) = 7.602 ns; Loc. = LC_X9_Y11_N3; Fanout = 4; REG Node = 'lcd:inst1\|clkcnt\[1\]'" {  } { { "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/" "" "4.452 ns" { div16:inst|count[3] lcd:inst1|clkcnt[1] } "NODE_NAME" } "" } } { "lcd.v" "" { Text "E:/code/EP1C6/S4_LCD_V/proj/lcd.v" 68 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.748 ns) + CELL(0.114 ns) 8.464 ns lcd:inst1\|reduce_nor~127 4 COMB LC_X8_Y11_N2 1 " "Info: 4: + IC(0.748 ns) + CELL(0.114 ns) = 8.464 ns; Loc. = LC_X8_Y11_N2; Fanout = 1; COMB Node = 'lcd:inst1\|reduce_nor~127'" {  } { { "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/" "" "0.862 ns" { lcd:inst1|clkcnt[1] lcd:inst1|reduce_nor~127 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.454 ns) + CELL(0.292 ns) 9.210 ns lcd:inst1\|reduce_nor~131 5 COMB LC_X8_Y11_N9 2 " "Info: 5: + IC(0.454 ns) + CELL(0.292 ns) = 9.210 ns; Loc. = LC_X8_Y11_N9; Fanout = 2; COMB Node = 'lcd:inst1\|reduce_nor~131'" {  } { { "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/" "" "0.746 ns" { lcd:inst1|reduce_nor~127 lcd:inst1|reduce_nor~131 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.480 ns) + CELL(0.935 ns) 10.625 ns lcd:inst1\|clkdiv 6 REG LC_X8_Y11_N6 3 " "Info: 6: + IC(0.480 ns) + CELL(0.935 ns) = 10.625 ns; Loc. = LC_X8_Y11_N6; Fanout = 3; REG Node = 'lcd:inst1\|clkdiv'" {  } { { "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/" "" "1.415 ns" { lcd:inst1|reduce_nor~131 lcd:inst1|clkdiv } "NODE_NAME" } "" } } { "lcd.v" "" { Text "E:/code/EP1C6/S4_LCD_V/proj/lcd.v" 84 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.035 ns) + CELL(0.935 ns) 15.595 ns lcd:inst1\|clk_int 7 REG LC_X10_Y10_N2 24 " "Info: 7: + IC(4.035 ns) + CELL(0.935 ns) = 15.595 ns; Loc. = LC_X10_Y10_N2; Fanout = 24; REG Node = 'lcd:inst1\|clk_int'" {  } { { "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/" "" "4.970 ns" { lcd:inst1|clkdiv lcd:inst1|clk_int } "NODE_NAME" } "" } } { "lcd.v" "" { Text "E:/code/EP1C6/S4_LCD_V/proj/lcd.v" 91 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.878 ns) + CELL(0.711 ns) 20.184 ns lcd:inst1\|state.SWITCHMODE 8 REG LC_X9_Y9_N4 3 " "Info: 8: + IC(3.878 ns) + CELL(0.711 ns) = 20.184 ns; Loc. = LC_X9_Y9_N4; Fanout = 3; REG Node = 'lcd:inst1\|state.SWITCHMODE'" {  } { { "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/" "" "4.589 ns" { lcd:inst1|clk_int lcd:inst1|state.SWITCHMODE } "NODE_NAME" } "" } } { "lcd.v" "" { Text "E:/code/EP1C6/S4_LCD_V/proj/lcd.v" 8 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.326 ns 31.34 % " "Info: Total cell delay = 6.326 ns ( 31.34 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "13.858 ns 68.66 % " "Info: Total interconnect delay = 13.858 ns ( 68.66 % )" {  } {  } 0}  } { { "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/" "" "20.184 ns" { mclk div16:inst|count[3] lcd:inst1|clkcnt[1] lcd:inst1|reduce_nor~127 lcd:inst1|reduce_nor~131 lcd:inst1|clkdiv lcd:inst1|clk_int lcd:inst1|state.SWITCHMODE } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "20.184 ns" { mclk mclk~out0 div16:inst|count[3] lcd:inst1|clkcnt[1] lcd:inst1|reduce_nor~127 lcd:inst1|reduce_nor~131 lcd:inst1|clkdiv lcd:inst1|clk_int lcd:inst1|state.SWITCHMODE } { 0.0ns 0.0ns 0.746ns 3.517ns 0.748ns 0.454ns 0.48ns 4.035ns 3.878ns } { 0.0ns 1.469ns 0.935ns 0.935ns 0.114ns 0.292ns 0.935ns 0.935ns 0.711ns } } }  } 0}  } { { "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/" "" "21.529 ns" { mclk div16:inst|count[3] lcd:inst1|clkcnt[11] lcd:inst1|reduce_nor~129 lcd:inst1|reduce_nor~131 lcd:inst1|clkdiv lcd:inst1|clk_int lcd:inst1|state.CLEAR } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "21.529 ns" { mclk mclk~out0 div16:inst|count[3] lcd:inst1|clkcnt[11] lcd:inst1|reduce_nor~129 lcd:inst1|reduce_nor~131 lcd:inst1|clkdiv lcd:inst1|clk_int lcd:inst1|state.CLEAR } { 0.0ns 0.0ns 0.746ns 3.515ns 1.524ns 0.399ns 0.48ns 4.035ns 3.878ns } { 0.0ns 1.469ns 0.935ns 0.935ns 0.59ns 0.442ns 0.935ns 0.935ns 0.711ns } } } { "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/" "" "20.184 ns" { mclk div16:inst|count[3] lcd:inst1|clkcnt[1] lcd:inst1|reduce_nor~127 lcd:inst1|reduce_nor~131 lcd:inst1|clkdiv lcd:inst1|clk_int lcd:inst1|state.SWITCHMODE } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "20.184 ns" { mclk mclk~out0 div16:inst|count[3] lcd:inst1|clkcnt[1] lcd:inst1|reduce_nor~127 lcd:inst1|reduce_nor~131 lcd:inst1|clkdiv lcd:inst1|clk_int lcd:inst1|state.SWITCHMODE } { 0.0ns 0.0ns 0.746ns 3.517ns 0.748ns 0.454ns 0.48ns 4.035ns 3.878ns } { 0.0ns 1.469ns 0.935ns 0.935ns 0.114ns 0.292ns 0.935ns 0.935ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "lcd.v" "" { Text "E:/code/EP1C6/S4_LCD_V/proj/lcd.v" 8 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.658 ns - Shortest register register " "Info: - Shortest register to register delay is 0.658 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lcd:inst1\|state.SWITCHMODE 1 REG LC_X9_Y9_N4 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X9_Y9_N4; Fanout = 3; REG Node = 'lcd:inst1\|state.SWITCHMODE'" {  } { { "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/" "" "" { lcd:inst1|state.SWITCHMODE } "NODE_NAME" } "" } } { "lcd.v" "" { Text "E:/code/EP1C6/S4_LCD_V/proj/lcd.v" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.543 ns) + CELL(0.115 ns) 0.658 ns lcd:inst1\|state.CLEAR 2 REG LC_X9_Y9_N8 2 " "Info: 2: + IC(0.543 ns) + CELL(0.115 ns) = 0.658 ns; Loc. = LC_X9_Y9_N8; Fanout = 2; REG Node = 'lcd:inst1\|state.CLEAR'" {  } { { "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/" "" "0.658 ns" { lcd:inst1|state.SWITCHMODE lcd:inst1|state.CLEAR } "NODE_NAME" } "" } } { "lcd.v" "" { Text "E:/code/EP1C6/S4_LCD_V/proj/lcd.v" 8 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.115 ns 17.48 % " "Info: Total cell delay = 0.115 ns ( 17.48 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.543 ns 82.52 % " "Info: Total interconnect delay = 0.543 ns ( 82.52 % )" {  } {  } 0}  } { { "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/" "" "0.658 ns" { lcd:inst1|state.SWITCHMODE lcd:inst1|state.CLEAR } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "0.658 ns" { lcd:inst1|state.SWITCHMODE lcd:inst1|state.CLEAR } { 0.0ns 0.543ns } { 0.0ns 0.115ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "lcd.v" "" { Text "E:/code/EP1C6/S4_LCD_V/proj/lcd.v" 8 -1 0 } }  } 0}  } { { "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/" "" "21.529 ns" { mclk div16:inst|count[3] lcd:inst1|clkcnt[11] lcd:inst1|reduce_nor~129 lcd:inst1|reduce_nor~131 lcd:inst1|clkdiv lcd:inst1|clk_int lcd:inst1|state.CLEAR } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "21.529 ns" { mclk mclk~out0 div16:inst|count[3] lcd:inst1|clkcnt[11] lcd:inst1|reduce_nor~129 lcd:inst1|reduce_nor~131 lcd:inst1|clkdiv lcd:inst1|clk_int lcd:inst1|state.CLEAR } { 0.0ns 0.0ns 0.746ns 3.515ns 1.524ns 0.399ns 0.48ns 4.035ns 3.878ns } { 0.0ns 1.469ns 0.935ns 0.935ns 0.59ns 0.442ns 0.935ns 0.935ns 0.711ns } } } { "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/" "" "20.184 ns" { mclk div16:inst|count[3] lcd:inst1|clkcnt[1] lcd:inst1|reduce_nor~127 lcd:inst1|reduce_nor~131 lcd:inst1|clkdiv lcd:inst1|clk_int lcd:inst1|state.SWITCHMODE } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "20.184 ns" { mclk mclk~out0 div16:inst|count[3] lcd:inst1|clkcnt[1] lcd:inst1|reduce_nor~127 lcd:inst1|reduce_nor~131 lcd:inst1|clkdiv lcd:inst1|clk_int lcd:inst1|state.SWITCHMODE } { 0.0ns 0.0ns 0.746ns 3.517ns 0.748ns 0.454ns 0.48ns 4.035ns 3.878ns } { 0.0ns 1.469ns 0.935ns 0.935ns 0.114ns 0.292ns 0.935ns 0.935ns 0.711ns } } } { "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/" "" "0.658 ns" { lcd:inst1|state.SWITCHMODE lcd:inst1|state.CLEAR } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "0.658 ns" { lcd:inst1|state.SWITCHMODE lcd:inst1|state.CLEAR } { 0.0ns 0.543ns } { 0.0ns 0.115ns } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "sld_hub:sld_hub_inst\|sld_dffex:IRF_ENA_0\|Q\[0\] altera_internal_jtag~TMSUTAP altera_internal_jtag~TCKUTAP -0.256 ns register " "Info: tsu for register \"sld_hub:sld_hub_inst\|sld_dffex:IRF_ENA_0\|Q\[0\]\" (data pin = \"altera_internal_jtag~TMSUTAP\", clock pin = \"altera_internal_jtag~TCKUTAP\") is -0.256 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.001 ns + Longest pin register " "Info: + Longest pin to register delay is 5.001 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TMSUTAP 1 PIN JTAG_X1_Y10_N1 22 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y10_N1; Fanout = 22; PIN Node = 'altera_internal_jtag~TMSUTAP'" {  } { { "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/" "" "" { altera_internal_jtag~TMSUTAP } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.267 ns) + CELL(0.590 ns) 2.857 ns sld_hub:sld_hub_inst\|IRF_ENA_ENABLE~21 2 COMB LC_X14_Y13_N9 2 " "Info: 2: + IC(2.267 ns) + CELL(0.590 ns) = 2.857 ns; Loc. = LC_X14_Y13_N9; Fanout = 2; COMB Node = 'sld_hub:sld_hub_inst\|IRF_ENA_ENABLE~21'" {  } { { "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/" "" "2.857 ns" { altera_internal_jtag~TMSUTAP sld_hub:sld_hub_inst|IRF_ENA_ENABLE~21 } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 371 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.277 ns) + CELL(0.867 ns) 5.001 ns sld_hub:sld_hub_inst\|sld_dffex:IRF_ENA_0\|Q\[0\] 3 REG LC_X13_Y10_N5 3 " "Info: 3: + IC(1.277 ns) + CELL(0.867 ns) = 5.001 ns; Loc. = LC_X13_Y10_N5; Fanout = 3; REG Node = 'sld_hub:sld_hub_inst\|sld_dffex:IRF_ENA_0\|Q\[0\]'" {  } { { "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/" "" "2.144 ns" { sld_hub:sld_hub_inst|IRF_ENA_ENABLE~21 sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0|Q[0] } "NODE_NAME" } "" } } { "sld_dffex.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.457 ns 29.13 % " "Info: Total cell delay = 1.457 ns ( 29.13 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.544 ns 70.87 % " "Info: Total interconnect delay = 3.544 ns ( 70.87 % )" {  } {  } 0}  } { { "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/" "" "5.001 ns" { altera_internal_jtag~TMSUTAP sld_hub:sld_hub_inst|IRF_ENA_ENABLE~21 sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0|Q[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.001 ns" { altera_internal_jtag~TMSUTAP sld_hub:sld_hub_inst|IRF_ENA_ENABLE~21 sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0|Q[0] } { 0.000ns 2.267ns 1.277ns } { 0.000ns 0.590ns 0.867ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "sld_dffex.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 5.294 ns - Shortest register " "Info: - Shortest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 5.294 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y10_N1 306 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y10_N1; Fanout = 306; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.583 ns) + CELL(0.711 ns) 5.294 ns sld_hub:sld_hub_inst\|sld_dffex:IRF_ENA_0\|Q\[0\] 2 REG LC_X13_Y10_N5 3 " "Info: 2: + IC(4.583 ns) + CELL(0.711 ns) = 5.294 ns; Loc. = LC_X13_Y10_N5; Fanout = 3; REG Node = 'sld_hub:sld_hub_inst\|sld_dffex:IRF_ENA_0\|Q\[0\]'" {  } { { "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/" "" "5.294 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0|Q[0] } "NODE_NAME" } "" } } { "sld_dffex.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns 13.43 % " "Info: Total cell delay = 0.711 ns ( 13.43 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.583 ns 86.57 % " "Info: Total interconnect delay = 4.583 ns ( 86.57 % )" {  } {  } 0}  } { { "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/" "" "5.294 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0|Q[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.294 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0|Q[0] } { 0.000ns 4.583ns } { 0.000ns 0.711ns } } }  } 0}  } { { "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/" "" "5.001 ns" { altera_internal_jtag~TMSUTAP sld_hub:sld_hub_inst|IRF_ENA_ENABLE~21 sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0|Q[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.001 ns" { altera_internal_jtag~TMSUTAP sld_hub:sld_hub_inst|IRF_ENA_ENABLE~21 sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0|Q[0] } { 0.000ns 2.267ns 1.277ns } { 0.000ns 0.590ns 0.867ns } } } { "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN"