lcd_v.tan.qmsg

我买的红色飓风FPGA,EP1C6开发板的配套USBA实验例程 LCD模块的程序

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "altera_internal_jtag~TCKUTAP register sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[3\] register sld_hub:sld_hub_inst\|hub_tdo 100.52 MHz 9.948 ns Internal " "Info: Clock \"altera_internal_jtag~TCKUTAP\" has Internal fmax of 100.52 MHz between source register \"sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[3\]\" and destination register \"sld_hub:sld_hub_inst\|hub_tdo\" (period= 9.948 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.704 ns + Longest register register " "Info: + Longest register to register delay is 4.704 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[3\] 1 REG LC_X19_Y13_N9 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X19_Y13_N9; Fanout = 3; REG Node = 'sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[3\]'" {  } { { "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/" "" "" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[3] } "NODE_NAME" } "" } } { "sld_dffex.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.374 ns) + CELL(0.590 ns) 1.964 ns sld_hub:sld_hub_inst\|hub_tdo~279 2 COMB LC_X16_Y13_N9 1 " "Info: 2: + IC(1.374 ns) + CELL(0.590 ns) = 1.964 ns; Loc. = LC_X16_Y13_N9; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~279'" {  } { { "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/" "" "1.964 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[3] sld_hub:sld_hub_inst|hub_tdo~279 } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.145 ns) + CELL(0.590 ns) 3.699 ns sld_hub:sld_hub_inst\|hub_tdo~280 3 COMB LC_X13_Y13_N0 1 " "Info: 3: + IC(1.145 ns) + CELL(0.590 ns) = 3.699 ns; Loc. = LC_X13_Y13_N0; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~280'" {  } { { "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/" "" "1.735 ns" { sld_hub:sld_hub_inst|hub_tdo~279 sld_hub:sld_hub_inst|hub_tdo~280 } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.398 ns) + CELL(0.607 ns) 4.704 ns sld_hub:sld_hub_inst\|hub_tdo 4 REG LC_X13_Y13_N3 0 " "Info: 4: + IC(0.398 ns) + CELL(0.607 ns) = 4.704 ns; Loc. = LC_X13_Y13_N3; Fanout = 0; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo'" {  } { { "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/" "" "1.005 ns" { sld_hub:sld_hub_inst|hub_tdo~280 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.787 ns 37.99 % " "Info: Total cell delay = 1.787 ns ( 37.99 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.917 ns 62.01 % " "Info: Total interconnect delay = 2.917 ns ( 62.01 % )" {  } {  } 0}  } { { "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/" "" "4.704 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[3] sld_hub:sld_hub_inst|hub_tdo~279 sld_hub:sld_hub_inst|hub_tdo~280 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.704 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[3] sld_hub:sld_hub_inst|hub_tdo~279 sld_hub:sld_hub_inst|hub_tdo~280 sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 1.374ns 1.145ns 0.398ns } { 0.000ns 0.590ns 0.590ns 0.607ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.009 ns - Smallest " "Info: - Smallest clock skew is -0.009 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 5.322 ns + Shortest register " "Info: + Shortest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 5.322 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y10_N1 306 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y10_N1; Fanout = 306; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.611 ns) + CELL(0.711 ns) 5.322 ns sld_hub:sld_hub_inst\|hub_tdo 2 REG LC_X13_Y13_N3 0 " "Info: 2: + IC(4.611 ns) + CELL(0.711 ns) = 5.322 ns; Loc. = LC_X13_Y13_N3; Fanout = 0; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo'" {  } { { "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/" "" "5.322 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns 13.36 % " "Info: Total cell delay = 0.711 ns ( 13.36 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.611 ns 86.64 % " "Info: Total interconnect delay = 4.611 ns ( 86.64 % )" {  } {  } 0}  } { { "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/" "" "5.322 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.322 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 4.611ns } { 0.000ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP source 5.331 ns - Longest register " "Info: - Longest clock path from clock \"altera_internal_jtag~TCKUTAP\" to source register is 5.331 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y10_N1 306 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y10_N1; Fanout = 306; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.620 ns) + CELL(0.711 ns) 5.331 ns sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[3\] 2 REG LC_X19_Y13_N9 3 " "Info: 2: + IC(4.620 ns) + CELL(0.711 ns) = 5.331 ns; Loc. = LC_X19_Y13_N9; Fanout = 3; REG Node = 'sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[3\]'" {  } { { "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/" "" "5.331 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[3] } "NODE_NAME" } "" } } { "sld_dffex.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns 13.34 % " "Info: Total cell delay = 0.711 ns ( 13.34 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.620 ns 86.66 % " "Info: Total interconnect delay = 4.620 ns ( 86.66 % )" {  } {  } 0}  } { { "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/" "" "5.331 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.331 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[3] } { 0.000ns 4.620ns } { 0.000ns 0.711ns } } }  } 0}  } { { "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/" "" "5.322 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.322 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 4.611ns } { 0.000ns 0.711ns } } } { "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/" "" "5.331 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.331 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[3] } { 0.000ns 4.620ns } { 0.000ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "sld_dffex.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "sld_hub.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "sld_dffex.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } } { "sld_hub.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0}  } { { "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/" "" "4.704 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[3] sld_hub:sld_hub_inst|hub_tdo~279 sld_hub:sld_hub_inst|hub_tdo~280 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.704 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[3] sld_hub:sld_hub_inst|hub_tdo~279 sld_hub:sld_hub_inst|hub_tdo~280 sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 1.374ns 1.145ns 0.398ns } { 0.000ns 0.590ns 0.590ns 0.607ns } } } { "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/" "" "5.322 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.322 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 4.611ns } { 0.000ns 0.711ns } } } { "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/" "" "5.331 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.331 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[3] } { 0.000ns 4.620ns } { 0.000ns 0.711ns } } }  } 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "mclk 17 " "Warning: Circuit may not operate. Detected 17 non-operational path(s) clocked by clock \"mclk\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0}