lcd_v.tan.qmsg

我买的红色飓风FPGA,EP1C6开发板的配套USBA实验例程 LCD模块的程序

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "23 " "Warning: Found 23 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "lcd:inst1\|clkcnt\[15\] " "Info: Detected ripple clock \"lcd:inst1\|clkcnt\[15\]\" as buffer" {  } { { "lcd.v" "" { Text "E:/code/EP1C6/S4_LCD_V/proj/lcd.v" 68 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst1\|clkcnt\[15\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst1\|clkcnt\[12\] " "Info: Detected ripple clock \"lcd:inst1\|clkcnt\[12\]\" as buffer" {  } { { "lcd.v" "" { Text "E:/code/EP1C6/S4_LCD_V/proj/lcd.v" 68 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst1\|clkcnt\[12\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst1\|clkcnt\[14\] " "Info: Detected ripple clock \"lcd:inst1\|clkcnt\[14\]\" as buffer" {  } { { "lcd.v" "" { Text "E:/code/EP1C6/S4_LCD_V/proj/lcd.v" 68 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst1\|clkcnt\[14\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst1\|clkcnt\[13\] " "Info: Detected ripple clock \"lcd:inst1\|clkcnt\[13\]\" as buffer" {  } { { "lcd.v" "" { Text "E:/code/EP1C6/S4_LCD_V/proj/lcd.v" 68 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst1\|clkcnt\[13\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst1\|clkcnt\[11\] " "Info: Detected ripple clock \"lcd:inst1\|clkcnt\[11\]\" as buffer" {  } { { "lcd.v" "" { Text "E:/code/EP1C6/S4_LCD_V/proj/lcd.v" 68 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst1\|clkcnt\[11\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst1\|clkcnt\[10\] " "Info: Detected ripple clock \"lcd:inst1\|clkcnt\[10\]\" as buffer" {  } { { "lcd.v" "" { Text "E:/code/EP1C6/S4_LCD_V/proj/lcd.v" 68 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst1\|clkcnt\[10\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst1\|clkcnt\[9\] " "Info: Detected ripple clock \"lcd:inst1\|clkcnt\[9\]\" as buffer" {  } { { "lcd.v" "" { Text "E:/code/EP1C6/S4_LCD_V/proj/lcd.v" 68 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst1\|clkcnt\[9\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst1\|clkcnt\[8\] " "Info: Detected ripple clock \"lcd:inst1\|clkcnt\[8\]\" as buffer" {  } { { "lcd.v" "" { Text "E:/code/EP1C6/S4_LCD_V/proj/lcd.v" 68 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst1\|clkcnt\[8\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst1\|clkcnt\[6\] " "Info: Detected ripple clock \"lcd:inst1\|clkcnt\[6\]\" as buffer" {  } { { "lcd.v" "" { Text "E:/code/EP1C6/S4_LCD_V/proj/lcd.v" 68 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst1\|clkcnt\[6\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst1\|clkcnt\[7\] " "Info: Detected ripple clock \"lcd:inst1\|clkcnt\[7\]\" as buffer" {  } { { "lcd.v" "" { Text "E:/code/EP1C6/S4_LCD_V/proj/lcd.v" 68 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst1\|clkcnt\[7\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst1\|clkcnt\[5\] " "Info: Detected ripple clock \"lcd:inst1\|clkcnt\[5\]\" as buffer" {  } { { "lcd.v" "" { Text "E:/code/EP1C6/S4_LCD_V/proj/lcd.v" 68 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst1\|clkcnt\[5\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst1\|clkcnt\[4\] " "Info: Detected ripple clock \"lcd:inst1\|clkcnt\[4\]\" as buffer" {  } { { "lcd.v" "" { Text "E:/code/EP1C6/S4_LCD_V/proj/lcd.v" 68 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst1\|clkcnt\[4\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst1\|clkcnt\[3\] " "Info: Detected ripple clock \"lcd:inst1\|clkcnt\[3\]\" as buffer" {  } { { "lcd.v" "" { Text "E:/code/EP1C6/S4_LCD_V/proj/lcd.v" 68 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst1\|clkcnt\[3\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst1\|clkcnt\[2\] " "Info: Detected ripple clock \"lcd:inst1\|clkcnt\[2\]\" as buffer" {  } { { "lcd.v" "" { Text "E:/code/EP1C6/S4_LCD_V/proj/lcd.v" 68 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst1\|clkcnt\[2\]" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "lcd:inst1\|reduce_nor~130 " "Info: Detected gated clock \"lcd:inst1\|reduce_nor~130\" as buffer" {  } { { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst1\|reduce_nor~130" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "lcd:inst1\|reduce_nor~127 " "Info: Detected gated clock \"lcd:inst1\|reduce_nor~127\" as buffer" {  } { { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst1\|reduce_nor~127" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "lcd:inst1\|reduce_nor~129 " "Info: Detected gated clock \"lcd:inst1\|reduce_nor~129\" as buffer" {  } { { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst1\|reduce_nor~129" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "lcd:inst1\|reduce_nor~128 " "Info: Detected gated clock \"lcd:inst1\|reduce_nor~128\" as buffer" {  } { { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst1\|reduce_nor~128" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst1\|clkcnt\[1\] " "Info: Detected ripple clock \"lcd:inst1\|clkcnt\[1\]\" as buffer" {  } { { "lcd.v" "" { Text "E:/code/EP1C6/S4_LCD_V/proj/lcd.v" 68 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst1\|clkcnt\[1\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "div16:inst\|count\[3\] " "Info: Detected ripple clock \"div16:inst\|count\[3\]\" as buffer" {  } { { "DIV16.v" "" { Text "E:/code/EP1C6/S4_LCD_V/proj/DIV16.v" 5 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "div16:inst\|count\[3\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst1\|clkcnt\[0\] " "Info: Detected ripple clock \"lcd:inst1\|clkcnt\[0\]\" as buffer" {  } { { "lcd.v" "" { Text "E:/code/EP1C6/S4_LCD_V/proj/lcd.v" 68 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst1\|clkcnt\[0\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst1\|clk_int " "Info: Detected ripple clock \"lcd:inst1\|clk_int\" as buffer" {  } { { "lcd.v" "" { Text "E:/code/EP1C6/S4_LCD_V/proj/lcd.v" 91 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst1\|clk_int" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst1\|clkdiv " "Info: Detected ripple clock \"lcd:inst1\|clkdiv\" as buffer" {  } { { "lcd.v" "" { Text "E:/code/EP1C6/S4_LCD_V/proj/lcd.v" 84 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst1\|clkdiv" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "mclk register lcd:inst1\|lcd_e register sld_signaltap:auto_signaltap_0\|acq_trigger_in_reg\[14\] 48.66 MHz 20.552 ns Internal " "Info: Clock \"mclk\" has Internal fmax of 48.66 MHz between source register \"lcd:inst1\|lcd_e\" and destination register \"sld_signaltap:auto_signaltap_0\|acq_trigger_in_reg\[14\]\" (period= 20.552 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.675 ns + Longest register register " "Info: + Longest register to register delay is 0.675 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lcd:inst1\|lcd_e 1 REG LC_X13_Y14_N2 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X13_Y14_N2; Fanout = 3; REG Node = 'lcd:inst1\|lcd_e'" {  } { { "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/" "" "" { lcd:inst1|lcd_e } "NODE_NAME" } "" } } { "lcd.v" "" { Text "E:/code/EP1C6/S4_LCD_V/proj/lcd.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.560 ns) + CELL(0.115 ns) 0.675 ns sld_signaltap:auto_signaltap_0\|acq_trigger_in_reg\[14\] 2 REG LC_X13_Y14_N0 5 " "Info: 2: + IC(0.560 ns) + CELL(0.115 ns) = 0.675 ns; Loc. = LC_X13_Y14_N0; Fanout = 5; REG Node = 'sld_signaltap:auto_signaltap_0\|acq_trigger_in_reg\[14\]'" {  } { { "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/" "" "0.675 ns" { lcd:inst1|lcd_e sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[14] } "NODE_NAME" } "" } } { "sld_signaltap.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 437 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.115 ns 17.04 % " "Info: Total cell delay = 0.115 ns ( 17.04 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.560 ns 82.96 % " "Info: Total interconnect delay = 0.560 ns ( 82.96 % )" {  } {  } 0}  } { { "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/" "" "0.675 ns" { lcd:inst1|lcd_e sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[14] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "0.675 ns" { lcd:inst1|lcd_e sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[14] } { 0.000ns 0.560ns } { 0.000ns 0.115ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-9.340 ns - Smallest " "Info: - Smallest clock skew is -9.340 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "mclk destination 7.408 ns + Shortest register " "Info: + Shortest clock path from clock \"mclk\" to destination register is 7.408 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns mclk 1 CLK PIN_153 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 4; CLK Node = 'mclk'" {  } { { "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/" "" "" { mclk } "NODE_NAME" } "" } } { "lcd_v.bdf" "" { Schematic "E:/code/EP1C6/S4_LCD_V/proj/lcd_v.bdf" { { 48 -96 72 64 "mclk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.746 ns) + CELL(0.935 ns) 3.150 ns div16:inst\|count\[3\] 2 REG LC_X8_Y10_N2 270 " "Info: 2: + IC(0.746 ns) + CELL(0.935 ns) = 3.150 ns; Loc. = LC_X8_Y10_N2; Fanout = 270; REG Node = 'div16:inst\|count\[3\]'" {  } { { "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/" "" "1.681 ns" { mclk div16:inst|count[3] } "NODE_NAME" } "" } } { "DIV16.v" "" { Text "E:/code/EP1C6/S4_LCD_V/proj/DIV16.v" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.547 ns) + CELL(0.711 ns) 7.408 ns sld_signaltap:auto_signaltap_0\|acq_trigger_in_reg\[14\] 3 REG LC_X13_Y14_N0 5 " "Info: 3: + IC(3.547 ns) + CELL(0.711 ns) = 7.408 ns; Loc. = LC_X13_Y14_N0; Fanout = 5; REG Node = 'sld_signaltap:auto_signaltap_0\|acq_trigger_in_reg\[14\]'" {  } { { "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/" "" "4.258 ns" { div16:inst|count[3] sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[14] } "NODE_NAME" } "" } } { "sld_signaltap.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 437 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns 42.05 % " "Info: Total cell delay = 3.115 ns ( 42.05 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.293 ns 57.95 % " "Info: Total interconnect delay = 4.293 ns ( 57.95 % )" {  } {  } 0}  } { { "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/" "" "7.408 ns" { mclk div16:inst|count[3] sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[14] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.408 ns" { mclk mclk~out0 div16:inst|count[3] sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[14] } { 0.000ns 0.000ns 0.746ns 3.547ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "mclk source 16.748 ns - Longest register " "Info: - Longest clock path from clock \"mclk\" to source register is 16.748 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns mclk 1 CLK PIN_153 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 4; CLK Node = 'mclk'" {  } { { "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/" "" "" { mclk } "NODE_NAME" } "" } } { "lcd_v.bdf" "" { Schematic "E:/code/EP1C6/S4_LCD_V/proj/lcd_v.bdf" { { 48 -96 72 64 "mclk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.746 ns) + CELL(0.935 ns) 3.150 ns div16:inst\|count\[3\] 2 REG LC_X8_Y10_N2 270 " "Info: 2: + IC(0.746 ns) + CELL(0.935 ns) = 3.150 ns; Loc. = LC_X8_Y10_N2; Fanout = 270; REG Node = 'div16:inst\|count\[3\]'" {  } { { "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/" "" "1.681 ns" { mclk div16:inst|count[3] } "NODE_NAME" } "" } } { "DIV16.v" "" { Text "E:/code/EP1C6/S4_LCD_V/proj/DIV16.v" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.515 ns) + CELL(0.935 ns) 7.600 ns lcd:inst1\|clkcnt\[11\] 3 REG LC_X9_Y10_N3 4 " "Info: 3: + IC(3.515 ns) + CELL(0.935 ns) = 7.600 ns; Loc. = LC_X9_Y10_N3; Fanout = 4; REG Node = 'lcd:inst1\|clkcnt\[11\]'" {  } { { "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/" "" "4.450 ns" { div16:inst|count[3] lcd:inst1|clkcnt[11] } "NODE_NAME" } "" } } { "lcd.v" "" { Text "E:/code/EP1C6/S4_LCD_V/proj/lcd.v" 68 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.524 ns) + CELL(0.590 ns) 9.714 ns lcd:inst1\|reduce_nor~129 4 COMB LC_X8_Y11_N5 1 " "Info: 4: + IC(1.524 ns) + CELL(0.590 ns) = 9.714 ns; Loc. = LC_X8_Y11_N5; Fanout = 1; COMB Node = 'lcd:inst1\|reduce_nor~129'" {  } { { "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/" "" "2.114 ns" { lcd:inst1|clkcnt[11] lcd:inst1|reduce_nor~129 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.399 ns) + CELL(0.442 ns) 10.555 ns lcd:inst1\|reduce_nor~131 5 COMB LC_X8_Y11_N9 2 " "Info: 5: + IC(0.399 ns) + CELL(0.442 ns) = 10.555 ns; Loc. = LC_X8_Y11_N9; Fanout = 2; COMB Node = 'lcd:inst1\|reduce_nor~131'" {  } { { "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/" "" "0.841 ns" { lcd:inst1|reduce_nor~129 lcd:inst1|reduce_nor~131 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.480 ns) + CELL(0.935 ns) 11.970 ns lcd:inst1\|clkdiv 6 REG LC_X8_Y11_N6 3 " "Info: 6: + IC(0.480 ns) + CELL(0.935 ns) = 11.970 ns; Loc. = LC_X8_Y11_N6; Fanout = 3; REG Node = 'lcd:inst1\|clkdiv'" {  } { { "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/" "" "1.415 ns" { lcd:inst1|reduce_nor~131 lcd:inst1|clkdiv } "NODE_NAME" } "" } } { "lcd.v" "" { Text "E:/code/EP1C6/S4_LCD_V/proj/lcd.v" 84 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.067 ns) + CELL(0.711 ns) 16.748 ns lcd:inst1\|lcd_e 7 REG LC_X13_Y14_N2 3 " "Info: 7: + IC(4.067 ns) + CELL(0.711 ns) = 16.748 ns; Loc. = LC_X13_Y14_N2; Fanout = 3; REG Node = 'lcd:inst1\|lcd_e'" {  } { { "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/" "" "4.778 ns" { lcd:inst1|clkdiv lcd:inst1|lcd_e } "NODE_NAME" } "" } } { "lcd.v" "" { Text "E:/code/EP1C6/S4_LCD_V/proj/lcd.v" 3 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.017 ns 35.93 % " "Info: Total cell delay = 6.017 ns ( 35.93 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.731 ns 64.07 % " "Info: Total interconnect delay = 10.731 ns ( 64.07 % )" {  } {  } 0}  } { { "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/" "" "16.748 ns" { mclk div16:inst|count[3] lcd:inst1|clkcnt[11] lcd:inst1|reduce_nor~129 lcd:inst1|reduce_nor~131 lcd:inst1|clkdiv lcd:inst1|lcd_e } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "16.748 ns" { mclk mclk~out0 div16:inst|count[3] lcd:inst1|clkcnt[11] lcd:inst1|reduce_nor~129 lcd:inst1|reduce_nor~131 lcd:inst1|clkdiv lcd:inst1|lcd_e } { 0.000ns 0.000ns 0.746ns 3.515ns 1.524ns 0.399ns 0.480ns 4.067ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.590ns 0.442ns 0.935ns 0.711ns } } }  } 0}  } { { "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/" "" "7.408 ns" { mclk div16:inst|count[3] sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[14] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.408 ns" { mclk mclk~out0 div16:inst|count[3] sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[14] } { 0.000ns 0.000ns 0.746ns 3.547ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/" "" "16.748 ns" { mclk div16:inst|count[3] lcd:inst1|clkcnt[11] lcd:inst1|reduce_nor~129 lcd:inst1|reduce_nor~131 lcd:inst1|clkdiv lcd:inst1|lcd_e } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "16.748 ns" { mclk mclk~out0 div16:inst|count[3] lcd:inst1|clkcnt[11] lcd:inst1|reduce_nor~129 lcd:inst1|reduce_nor~131 lcd:inst1|clkdiv lcd:inst1|lcd_e } { 0.000ns 0.000ns 0.746ns 3.515ns 1.524ns 0.399ns 0.480ns 4.067ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.590ns 0.442ns 0.935ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "lcd.v" "" { Text "E:/code/EP1C6/S4_LCD_V/proj/lcd.v" 3 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "sld_signaltap.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 437 -1 0 } }  } 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "lcd.v" "" { Text "E:/code/EP1C6/S4_LCD_V/proj/lcd.v" 3 -1 0 } } { "sld_signaltap.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 437 -1 0 } }  } 0}  } { { "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/" "" "0.675 ns" { lcd:inst1|lcd_e sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[14] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "0.675 ns" { lcd:inst1|lcd_e sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[14] } { 0.000ns 0.560ns } { 0.000ns 0.115ns } } } { "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/" "" "7.408 ns" { mclk div16:inst|count[3] sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[14] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.408 ns" { mclk mclk~out0 div16:inst|count[3] sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[14] } { 0.000ns 0.000ns 0.746ns 3.547ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" "" { Report "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v_cmp.qrpt" Compiler "lcd_v" "UNKNOWN" "V1" "E:/code/EP1C6/S4_LCD_V/proj/db/lcd_v.quartus_db" { Floorplan "E:/code/EP1C6/S4_LCD_V/proj/" "" "16.748 ns" { mclk div16:inst|count[3] lcd:inst1|clkcnt[11] lcd:inst1|reduce_nor~129 lcd:inst1|reduce_nor~131 lcd:inst1|clkdiv lcd:inst1|lcd_e } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "16.748 ns" { mclk mclk~out0 div16:inst|count[3] lcd:inst1|clkcnt[11] lcd:inst1|reduce_nor~129 lcd:inst1|reduce_nor~131 lcd:inst1|clkdiv lcd:inst1|lcd_e } { 0.000ns 0.000ns 0.746ns 3.515ns 1.524ns 0.399ns 0.480ns 4.067ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.590ns 0.442ns 0.935ns 0.711ns } } }  } 0}