pc2fpga.tan.qmsg

我买的红色飓风FPGA,EP1C6开发板的配套USBA实验例程 use输出模块的程序

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "../Src/pc2fpga.v" "" { Text "E:/code/EP1C6/T3_USB_OUT/Src/pc2fpga.v" 14 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "altera_internal_jtag~TCKUTAP " "Info: Assuming node \"altera_internal_jtag~TCKUTAP\" is an undefined clock" {  } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "altera_internal_jtag~TCKUTAP" } } } }  } 0}  } {  } 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "clkin " "Info: Detected ripple clock \"clkin\" as buffer" {  } { { "../Src/pc2fpga.v" "" { Text "E:/code/EP1C6/T3_USB_OUT/Src/pc2fpga.v" 31 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clkin" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_counter:\\non_zero_sample_depth_gen:segment_addr_counter\|cntr_e29:auto_generated\|safe_q\[7\] register sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|segment_write_addr_adv_ena 127.23 MHz 7.86 ns Internal " "Info: Clock \"clk\" has Internal fmax of 127.23 MHz between source register \"sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_counter:\\non_zero_sample_depth_gen:segment_addr_counter\|cntr_e29:auto_generated\|safe_q\[7\]\" and destination register \"sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|segment_write_addr_adv_ena\" (period= 7.86 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.590 ns + Longest register register " "Info: + Longest register to register delay is 7.590 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_counter:\\non_zero_sample_depth_gen:segment_addr_counter\|cntr_e29:auto_generated\|safe_q\[7\] 1 REG LC_X20_Y7_N7 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X20_Y7_N7; Fanout = 4; REG Node = 'sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_counter:\\non_zero_sample_depth_gen:segment_addr_counter\|cntr_e29:auto_generated\|safe_q\[7\]'" {  } { { "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "E:/code/EP1C6/T3_USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "E:/code/EP1C6/T3_USB_OUT/Proj/" "" "" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_e29:auto_generated|safe_q[7] } "NODE_NAME" } "" } } { "db/cntr_e29.tdf" "" { Text "E:/code/EP1C6/T3_USB_OUT/Proj/db/cntr_e29.tdf" 120 8 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.780 ns) + CELL(0.590 ns) 1.370 ns sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_compare:\\non_zero_sample_depth_gen:segment_addr_compare\|comptree:comparator\|cmpchain:cmp_end\|comptree:comp\|cmpchain:cmp\[3\]\|_~1 2 COMB LC_X19_Y7_N0 1 " "Info: 2: + IC(0.780 ns) + CELL(0.590 ns) = 1.370 ns; Loc. = LC_X19_Y7_N0; Fanout = 1; COMB Node = 'sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_compare:\\non_zero_sample_depth_gen:segment_addr_compare\|comptree:comparator\|cmpchain:cmp_end\|comptree:comp\|cmpchain:cmp\[3\]\|_~1'" {  } { { "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "E:/code/EP1C6/T3_USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "E:/code/EP1C6/T3_USB_OUT/Proj/" "" "1.370 ns" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_e29:auto_generated|safe_q[7] sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|comptree:comparator|cmpchain:cmp_end|comptree:comp|cmpchain:cmp[3]|_~1 } "NODE_NAME" } "" } } { "comptree.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/comptree.tdf" 131 7 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.723 ns) + CELL(0.590 ns) 2.683 ns sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_compare:\\non_zero_sample_depth_gen:segment_addr_compare\|comptree:comparator\|cmpchain:cmp_end\|comptree:comp\|comptree:sub_comptree\|comptree:sub_comptree\|cmpchain:cmp_end\|aeb_out~62 3 COMB LC_X19_Y7_N9 1 " "Info: 3: + IC(0.723 ns) + CELL(0.590 ns) = 2.683 ns; Loc. = LC_X19_Y7_N9; Fanout = 1; COMB Node = 'sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_compare:\\non_zero_sample_depth_gen:segment_addr_compare\|comptree:comparator\|cmpchain:cmp_end\|comptree:comp\|comptree:sub_comptree\|comptree:sub_comptree\|cmpchain:cmp_end\|aeb_out~62'" {  } { { "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "E:/code/EP1C6/T3_USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "E:/code/EP1C6/T3_USB_OUT/Proj/" "" "1.313 ns" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|comptree:comparator|cmpchain:cmp_end|comptree:comp|cmpchain:cmp[3]|_~1 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|comptree:sub_comptree|cmpchain:cmp_end|aeb_out~62 } "NODE_NAME" } "" } } { "cmpchain.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/cmpchain.tdf" 116 6 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.117 ns) + CELL(0.590 ns) 4.390 ns sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_compare:\\non_zero_sample_depth_gen:segment_addr_compare\|comptree:comparator\|cmpchain:cmp_end\|comptree:comp\|comptree:sub_comptree\|comptree:sub_comptree\|cmpchain:cmp_end\|aeb_out~0 4 COMB LC_X19_Y7_N1 11 " "Info: 4: + IC(1.117 ns) + CELL(0.590 ns) = 4.390 ns; Loc. = LC_X19_Y7_N1; Fanout = 11; COMB Node = 'sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_compare:\\non_zero_sample_depth_gen:segment_addr_compare\|comptree:comparator\|cmpchain:cmp_end\|comptree:comp\|comptree:sub_comptree\|comptree:sub_comptree\|cmpchain:cmp_end\|aeb_out~0'" {  } { { "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "E:/code/EP1C6/T3_USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "E:/code/EP1C6/T3_USB_OUT/Proj/" "" "1.707 ns" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|comptree:sub_comptree|cmpchain:cmp_end|aeb_out~62 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|comptree:sub_comptree|cmpchain:cmp_end|aeb_out~0 } "NODE_NAME" } "" } } { "cmpchain.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/cmpchain.tdf" 116 6 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.462 ns) + CELL(0.738 ns) 7.590 ns sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|segment_write_addr_adv_ena 5 REG LC_X14_Y7_N5 12 " "Info: 5: + IC(2.462 ns) + CELL(0.738 ns) = 7.590 ns; Loc. = LC_X14_Y7_N5; Fanout = 12; REG Node = 'sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|segment_write_addr_adv_ena'" {  } { { "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "E:/code/EP1C6/T3_USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "E:/code/EP1C6/T3_USB_OUT/Proj/" "" "3.200 ns" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|comptree:sub_comptree|cmpchain:cmp_end|aeb_out~0 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena } "NODE_NAME" } "" } } { "sld_ela_control.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_ela_control.vhd" 1399 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.508 ns 33.04 % " "Info: Total cell delay = 2.508 ns ( 33.04 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.082 ns 66.96 % " "Info: Total interconnect delay = 5.082 ns ( 66.96 % )" {  } {  } 0}  } { { "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "E:/code/EP1C6/T3_USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "E:/code/EP1C6/T3_USB_OUT/Proj/" "" "7.590 ns" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_e29:auto_generated|safe_q[7] sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|comptree:comparator|cmpchain:cmp_end|comptree:comp|cmpchain:cmp[3]|_~1 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|comptree:sub_comptree|cmpchain:cmp_end|aeb_out~62 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|comptree:sub_comptree|cmpchain:cmp_end|aeb_out~0 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.590 ns" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_e29:auto_generated|safe_q[7] sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|comptree:comparator|cmpchain:cmp_end|comptree:comp|cmpchain:cmp[3]|_~1 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|comptree:sub_comptree|cmpchain:cmp_end|aeb_out~62 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|comptree:sub_comptree|cmpchain:cmp_end|aeb_out~0 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena } { 0.000ns 0.780ns 0.723ns 1.117ns 2.462ns } { 0.000ns 0.590ns 0.590ns 0.590ns 0.738ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.009 ns - Smallest " "Info: - Smallest clock skew is -0.009 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 8.888 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 8.888 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_153 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 1; CLK Node = 'clk'" {  } { { "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "E:/code/EP1C6/T3_USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "E:/code/EP1C6/T3_USB_OUT/Proj/" "" "" { clk } "NODE_NAME" } "" } } { "../Src/pc2fpga.v" "" { Text "E:/code/EP1C6/T3_USB_OUT/Src/pc2fpga.v" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.284 ns) + CELL(0.935 ns) 4.688 ns clkin 2 REG LC_X8_Y10_N2 176 " "Info: 2: + IC(2.284 ns) + CELL(0.935 ns) = 4.688 ns; Loc. = LC_X8_Y10_N2; Fanout = 176; REG Node = 'clkin'" {  } { { "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "E:/code/EP1C6/T3_USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "E:/code/EP1C6/T3_USB_OUT/Proj/" "" "3.219 ns" { clk clkin } "NODE_NAME" } "" } } { "../Src/pc2fpga.v" "" { Text "E:/code/EP1C6/T3_USB_OUT/Src/pc2fpga.v" 31 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.489 ns) + CELL(0.711 ns) 8.888 ns sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|segment_write_addr_adv_ena 3 REG LC_X14_Y7_N5 12 " "Info: 3: + IC(3.489 ns) + CELL(0.711 ns) = 8.888 ns; Loc. = LC_X14_Y7_N5; Fanout = 12; REG Node = 'sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|segment_write_addr_adv_ena'" {  } { { "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "E:/code/EP1C6/T3_USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "E:/code/EP1C6/T3_USB_OUT/Proj/" "" "4.200 ns" { clkin sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena } "NODE_NAME" } "" } } { "sld_ela_control.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_ela_control.vhd" 1399 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns 35.05 % " "Info: Total cell delay = 3.115 ns ( 35.05 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.773 ns 64.95 % " "Info: Total interconnect delay = 5.773 ns ( 64.95 % )" {  } {  } 0}  } { { "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "E:/code/EP1C6/T3_USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "E:/code/EP1C6/T3_USB_OUT/Proj/" "" "8.888 ns" { clk clkin sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.888 ns" { clk clk~out0 clkin sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena } { 0.000ns 0.000ns 2.284ns 3.489ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 8.897 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 8.897 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_153 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 1; CLK Node = 'clk'" {  } { { "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "E:/code/EP1C6/T3_USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "E:/code/EP1C6/T3_USB_OUT/Proj/" "" "" { clk } "NODE_NAME" } "" } } { "../Src/pc2fpga.v" "" { Text "E:/code/EP1C6/T3_USB_OUT/Src/pc2fpga.v" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.284 ns) + CELL(0.935 ns) 4.688 ns clkin 2 REG LC_X8_Y10_N2 176 " "Info: 2: + IC(2.284 ns) + CELL(0.935 ns) = 4.688 ns; Loc. = LC_X8_Y10_N2; Fanout = 176; REG Node = 'clkin'" {  } { { "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "E:/code/EP1C6/T3_USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "E:/code/EP1C6/T3_USB_OUT/Proj/" "" "3.219 ns" { clk clkin } "NODE_NAME" } "" } } { "../Src/pc2fpga.v" "" { Text "E:/code/EP1C6/T3_USB_OUT/Src/pc2fpga.v" 31 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.498 ns) + CELL(0.711 ns) 8.897 ns sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_counter:\\non_zero_sample_depth_gen:segment_addr_counter\|cntr_e29:auto_generated\|safe_q\[7\] 3 REG LC_X20_Y7_N7 4 " "Info: 3: + IC(3.498 ns) + CELL(0.711 ns) = 8.897 ns; Loc. = LC_X20_Y7_N7; Fanout = 4; REG Node = 'sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_counter:\\non_zero_sample_depth_gen:segment_addr_counter\|cntr_e29:auto_generated\|safe_q\[7\]'" {  } { { "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "E:/code/EP1C6/T3_USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "E:/code/EP1C6/T3_USB_OUT/Proj/" "" "4.209 ns" { clkin sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_e29:auto_generated|safe_q[7] } "NODE_NAME" } "" } } { "db/cntr_e29.tdf" "" { Text "E:/code/EP1C6/T3_USB_OUT/Proj/db/cntr_e29.tdf" 120 8 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns 35.01 % " "Info: Total cell delay = 3.115 ns ( 35.01 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.782 ns 64.99 % " "Info: Total interconnect delay = 5.782 ns ( 64.99 % )" {  } {  } 0}  } { { "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "E:/code/EP1C6/T3_USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "E:/code/EP1C6/T3_USB_OUT/Proj/" "" "8.897 ns" { clk clkin sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_e29:auto_generated|safe_q[7] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.897 ns" { clk clk~out0 clkin sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_e29:auto_generated|safe_q[7] } { 0.000ns 0.000ns 2.284ns 3.498ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0}  } { { "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "E:/code/EP1C6/T3_USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "E:/code/EP1C6/T3_USB_OUT/Proj/" "" "8.888 ns" { clk clkin sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.888 ns" { clk clk~out0 clkin sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena } { 0.000ns 0.000ns 2.284ns 3.489ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "E:/code/EP1C6/T3_USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "E:/code/EP1C6/T3_USB_OUT/Proj/" "" "8.897 ns" { clk clkin sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_e29:auto_generated|safe_q[7] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.897 ns" { clk clk~out0 clkin sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_e29:auto_generated|safe_q[7] } { 0.000ns 0.000ns 2.284ns 3.498ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "db/cntr_e29.tdf" "" { Text "E:/code/EP1C6/T3_USB_OUT/Proj/db/cntr_e29.tdf" 120 8 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "sld_ela_control.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_ela_control.vhd" 1399 -1 0 } }  } 0}  } { { "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "E:/code/EP1C6/T3_USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "E:/code/EP1C6/T3_USB_OUT/Proj/" "" "7.590 ns" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_e29:auto_generated|safe_q[7] sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|comptree:comparator|cmpchain:cmp_end|comptree:comp|cmpchain:cmp[3]|_~1 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|comptree:sub_comptree|cmpchain:cmp_end|aeb_out~62 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|comptree:sub_comptree|cmpchain:cmp_end|aeb_out~0 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.590 ns" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_e29:auto_generated|safe_q[7] sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|comptree:comparator|cmpchain:cmp_end|comptree:comp|cmpchain:cmp[3]|_~1 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|comptree:sub_comptree|cmpchain:cmp_end|aeb_out~62 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|comptree:sub_comptree|cmpchain:cmp_end|aeb_out~0 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena } { 0.000ns 0.780ns 0.723ns 1.117ns 2.462ns } { 0.000ns 0.590ns 0.590ns 0.590ns 0.738ns } } } { "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "E:/code/EP1C6/T3_USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "E:/code/EP1C6/T3_USB_OUT/Proj/" "" "8.888 ns" { clk clkin sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.888 ns" { clk clk~out0 clkin sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena } { 0.000ns 0.000ns 2.284ns 3.489ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "E:/code/EP1C6/T3_USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "E:/code/EP1C6/T3_USB_OUT/Proj/" "" "8.897 ns" { clk clkin sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_e29:auto_generated|safe_q[7] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.897 ns" { clk clk~out0 clkin sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_e29:auto_generated|safe_q[7] } { 0.000ns 0.000ns 2.284ns 3.498ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0}