pc2fpga.fit.qmsg

我买的红色飓风FPGA,EP1C6开发板的配套USBA实验例程 use输出模块的程序

{ "Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "3.719 ns register register " "Info: Estimated most critical path is register to register delay of 3.719 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_hub:sld_hub_inst\|sld_rom_sr:HUB_INFO_REG\|WORD_SR\[0\] 1 REG LAB_X12_Y10 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X12_Y10; Fanout = 1; REG Node = 'sld_hub:sld_hub_inst\|sld_rom_sr:HUB_INFO_REG\|WORD_SR\[0\]'" {  } { { "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "E:/code/EP1C6/T3_USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "E:/code/EP1C6/T3_USB_OUT/Proj/" "" "" { sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] } "NODE_NAME" } "" } } { "sld_rom_sr.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_rom_sr.vhd" 33 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.929 ns) + CELL(0.590 ns) 1.519 ns sld_hub:sld_hub_inst\|hub_tdo~277 2 COMB LAB_X11_Y8 1 " "Info: 2: + IC(0.929 ns) + CELL(0.590 ns) = 1.519 ns; Loc. = LAB_X11_Y8; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~277'" {  } { { "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "E:/code/EP1C6/T3_USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "E:/code/EP1C6/T3_USB_OUT/Proj/" "" "1.519 ns" { sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] sld_hub:sld_hub_inst|hub_tdo~277 } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.929 ns) + CELL(0.442 ns) 2.890 ns sld_hub:sld_hub_inst\|hub_tdo~278 3 COMB LAB_X12_Y9 1 " "Info: 3: + IC(0.929 ns) + CELL(0.442 ns) = 2.890 ns; Loc. = LAB_X12_Y9; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~278'" {  } { { "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "E:/code/EP1C6/T3_USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "E:/code/EP1C6/T3_USB_OUT/Proj/" "" "1.371 ns" { sld_hub:sld_hub_inst|hub_tdo~277 sld_hub:sld_hub_inst|hub_tdo~278 } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.222 ns) + CELL(0.607 ns) 3.719 ns sld_hub:sld_hub_inst\|hub_tdo 4 REG LAB_X12_Y9 0 " "Info: 4: + IC(0.222 ns) + CELL(0.607 ns) = 3.719 ns; Loc. = LAB_X12_Y9; Fanout = 0; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo'" {  } { { "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "E:/code/EP1C6/T3_USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "E:/code/EP1C6/T3_USB_OUT/Proj/" "" "0.829 ns" { sld_hub:sld_hub_inst|hub_tdo~278 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.639 ns 44.07 % " "Info: Total cell delay = 1.639 ns ( 44.07 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.080 ns 55.93 % " "Info: Total interconnect delay = 2.080 ns ( 55.93 % )" {  } {  } 0}  } { { "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "E:/code/EP1C6/T3_USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "E:/code/EP1C6/T3_USB_OUT/Proj/" "" "3.719 ns" { sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] sld_hub:sld_hub_inst|hub_tdo~277 sld_hub:sld_hub_inst|hub_tdo~278 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "1 7 " "Info: Average interconnect usage is 1% of the available device resources. Peak interconnect usage is 7%." {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements" {  } {  } 0}
{ "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE_TOP_MSG" "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\] " "Info: Node sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\] uses non-global routing resources to route signals to global destination nodes" { { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_hub:sld_hub_inst\|jtag_debug_mode_usr0 " "Info: Port clear -- assigned as a global for destination node sld_hub:sld_hub_inst\|jtag_debug_mode_usr0 -- routed using non-global resources" {  } { { "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "E:/code/EP1C6/T3_USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "E:/code/EP1C6/T3_USB_OUT/Proj/" "" "" { sld_hub:sld_hub_inst|jtag_debug_mode_usr0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|jtag_debug_mode_usr0" } } } } { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 380 -1 0 } } { "E:/code/EP1C6/T3_USB_OUT/Proj/pc2fpga.fld" "" { Floorplan "E:/code/EP1C6/T3_USB_OUT/Proj/pc2fpga.fld" "" "" { sld_hub:sld_hub_inst|jtag_debug_mode_usr0 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_hub:sld_hub_inst\|jtag_debug_mode_usr1 " "Info: Port clear -- assigned as a global for destination node sld_hub:sld_hub_inst\|jtag_debug_mode_usr1 -- routed using non-global resources" {  } { { "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "E:/code/EP1C6/T3_USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "E:/code/EP1C6/T3_USB_OUT/Proj/" "" "" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|jtag_debug_mode_usr1" } } } } { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 381 -1 0 } } { "E:/code/EP1C6/T3_USB_OUT/Proj/pc2fpga.fld" "" { Floorplan "E:/code/EP1C6/T3_USB_OUT/Proj/pc2fpga.fld" "" "" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } "NODE_NAME" } }  } 0}  } { { "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "E:/code/EP1C6/T3_USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "E:/code/EP1C6/T3_USB_OUT/Proj/" "" "" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\]" } } } } { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 1014 -1 0 } } { "E:/code/EP1C6/T3_USB_OUT/Proj/pc2fpga.fld" "" { Floorplan "E:/code/EP1C6/T3_USB_OUT/Proj/pc2fpga.fld" "" "" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[0] } "NODE_NAME" } }  } 0}
{ "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE_TOP_MSG" "sld_signaltap:auto_signaltap_0\|reset_all " "Info: Node sld_signaltap:auto_signaltap_0\|reset_all uses non-global routing resources to route signals to global destination nodes" { { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_signaltap:auto_signaltap_0\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:ram_data_shift_out\|dffs\[2\] " "Info: Port clear -- assigned as a global for destination node sld_signaltap:auto_signaltap_0\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:ram_data_shift_out\|dffs\[2\] -- routed using non-global resources" {  } { { "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "E:/code/EP1C6/T3_USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "E:/code/EP1C6/T3_USB_OUT/Proj/" "" "" { sld_signaltap:auto_signaltap_0|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sld_signaltap:auto_signaltap_0\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:ram_data_shift_out\|dffs\[2\]" } } } } { "lpm_shiftreg.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_shiftreg.tdf" 54 7 0 } } { "E:/code/EP1C6/T3_USB_OUT/Proj/pc2fpga.fld" "" { Floorplan "E:/code/EP1C6/T3_USB_OUT/Proj/pc2fpga.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[2] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_signaltap:auto_signaltap_0\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:ram_data_shift_out\|dffs\[1\] " "Info: Port clear -- assigned as a global for destination node sld_signaltap:auto_signaltap_0\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:ram_data_shift_out\|dffs\[1\] -- routed using non-global resources" {  } { { "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "E:/code/EP1C6/T3_USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "E:/code/EP1C6/T3_USB_OUT/Proj/" "" "" { sld_signaltap:auto_signaltap_0|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sld_signaltap:auto_signaltap_0\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:ram_data_shift_out\|dffs\[1\]" } } } } { "lpm_shiftreg.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_shiftreg.tdf" 54 7 0 } } { "E:/code/EP1C6/T3_USB_OUT/Proj/pc2fpga.fld" "" { Floorplan "E:/code/EP1C6/T3_USB_OUT/Proj/pc2fpga.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[1] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_signaltap:auto_signaltap_0\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:ram_data_shift_out\|dffs\[0\] " "Info: Port clear -- assigned as a global for destination node sld_signaltap:auto_signaltap_0\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:ram_data_shift_out\|dffs\[0\] -- routed using non-global resources" {  } { { "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "E:/code/EP1C6/T3_USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "E:/code/EP1C6/T3_USB_OUT/Proj/" "" "" { sld_signaltap:auto_signaltap_0|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sld_signaltap:auto_signaltap_0\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:ram_data_shift_out\|dffs\[0\]" } } } } { "lpm_shiftreg.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_shiftreg.tdf" 54 7 0 } } { "E:/code/EP1C6/T3_USB_OUT/Proj/pc2fpga.fld" "" { Floorplan "E:/code/EP1C6/T3_USB_OUT/Proj/pc2fpga.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[0] } "NODE_NAME" } }  } 0}  } { { "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "E:/code/EP1C6/T3_USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "E:/code/EP1C6/T3_USB_OUT/Proj/" "" "" { sld_signaltap:auto_signaltap_0|reset_all } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sld_signaltap:auto_signaltap_0\|reset_all" } } } } { "sld_signaltap.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 415 -1 0 } } { "E:/code/EP1C6/T3_USB_OUT/Proj/pc2fpga.fld" "" { Floorplan "E:/code/EP1C6/T3_USB_OUT/Proj/pc2fpga.fld" "" "" { sld_signaltap:auto_signaltap_0|reset_all } "NODE_NAME" } }  } 0}
{ "Warning" "WFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "1 " "Warning: The following 1 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "fifo_wr VCC " "Info: Pin fifo_wr has VCC driving its datain port" {  } { { "../Src/pc2fpga.v" "" { Text "E:/code/EP1C6/T3_USB_OUT/Src/pc2fpga.v" 18 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "fifo_wr" } } } } { "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" "" { Report "E:/code/EP1C6/T3_USB_OUT/Proj/db/pc2fpga_cmp.qrpt" Compiler "pc2fpga" "UNKNOWN" "V1" "E:/code/EP1C6/T3_USB_OUT/Proj/db/USB_OUT.quartus_db" { Floorplan "E:/code/EP1C6/T3_USB_OUT/Proj/" "" "" { fifo_wr } "NODE_NAME" } "" } } { "E:/code/EP1C6/T3_USB_OUT/Proj/pc2fpga.fld" "" { Floorplan "E:/code/EP1C6/T3_USB_OUT/Proj/pc2fpga.fld" "" "" { fifo_wr } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Feb 23 10:23:29 2006 " "Info: Processing ended: Thu Feb 23 10:23:29 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Info: Elapsed time: 00:00:08" {  } {  } 0}  } {  } 0}