fpga2pc.fit.qmsg

来自「我买的红色飓风FPGA,EP1C6开发板的配套USBA实验例程 use输入模块的」· QMSG 代码 · 共 38 行

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version " "Info: Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Feb 23 15:01:16 2006 " "Info: Processing started: Thu Feb 23 15:01:16 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off USB_IN -c fpga2pc " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off USB_IN -c fpga2pc" {  } {  } 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "fpga2pc EP1C6Q240C8 " "Info: Selected device EP1C6Q240C8 for design \"fpga2pc\"" {  } {  } 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. " { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C12Q240C8 " "Info: Device EP1C12Q240C8 is compatible" {  } {  } 2}  } {  } 2}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1 MHz " "Info: Assuming a global fmax requirement of 1 MHz" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources." {  } {  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "clkin Global clock " "Info: Automatically promoted some destinations of signal \"clkin\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "clkin " "Info: Destination \"clkin\" may be non-global or may not use global clock" {  } { { "../Src/fpga2pc.v" "" { Text "E:/code/EP1C6/T2_USB_IN/Src/fpga2pc.v" 32 -1 0 } }  } 0}  } { { "../Src/fpga2pc.v" "" { Text "E:/code/EP1C6/T2_USB_IN/Src/fpga2pc.v" 32 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "rst Global clock in PIN 131 " "Info: Automatically promoted signal \"rst\" to use Global clock in PIN 131" {  } { { "../Src/fpga2pc.v" "" { Text "E:/code/EP1C6/T2_USB_IN/Src/fpga2pc.v" 13 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "2.441 ns register register " "Info: Estimated most critical path is register to register delay of 2.441 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns fifo_data\[0\]~reg0 1 REG LAB_X2_Y9 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X2_Y9; Fanout = 4; REG Node = 'fifo_data\[0\]~reg0'" {  } { { "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "E:/code/EP1C6/T2_USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "E:/code/EP1C6/T2_USB_IN/Proj/" "" "" { fifo_data[0]~reg0 } "NODE_NAME" } "" } } { "../Src/fpga2pc.v" "" { Text "E:/code/EP1C6/T2_USB_IN/Src/fpga2pc.v" 74 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.470 ns) + CELL(0.575 ns) 1.045 ns fifo_data\[0\]~93COUT1_125 2 COMB LAB_X2_Y9 2 " "Info: 2: + IC(0.470 ns) + CELL(0.575 ns) = 1.045 ns; Loc. = LAB_X2_Y9; Fanout = 2; COMB Node = 'fifo_data\[0\]~93COUT1_125'" {  } { { "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "E:/code/EP1C6/T2_USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "E:/code/EP1C6/T2_USB_IN/Proj/" "" "1.045 ns" { fifo_data[0]~reg0 fifo_data[0]~93COUT1_125 } "NODE_NAME" } "" } } { "../Src/fpga2pc.v" "" { Text "E:/code/EP1C6/T2_USB_IN/Src/fpga2pc.v" 17 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.125 ns fifo_data\[1\]~97COUT1_126 3 COMB LAB_X2_Y9 2 " "Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 1.125 ns; Loc. = LAB_X2_Y9; Fanout = 2; COMB Node = 'fifo_data\[1\]~97COUT1_126'" {  } { { "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "E:/code/EP1C6/T2_USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "E:/code/EP1C6/T2_USB_IN/Proj/" "" "0.080 ns" { fifo_data[0]~93COUT1_125 fifo_data[1]~97COUT1_126 } "NODE_NAME" } "" } } { "../Src/fpga2pc.v" "" { Text "E:/code/EP1C6/T2_USB_IN/Src/fpga2pc.v" 17 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.205 ns fifo_data\[2\]~101COUT1_127 4 COMB LAB_X2_Y9 2 " "Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 1.205 ns; Loc. = LAB_X2_Y9; Fanout = 2; COMB Node = 'fifo_data\[2\]~101COUT1_127'" {  } { { "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "E:/code/EP1C6/T2_USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "E:/code/EP1C6/T2_USB_IN/Proj/" "" "0.080 ns" { fifo_data[1]~97COUT1_126 fifo_data[2]~101COUT1_127 } "NODE_NAME" } "" } } { "../Src/fpga2pc.v" "" { Text "E:/code/EP1C6/T2_USB_IN/Src/fpga2pc.v" 17 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.285 ns fifo_data\[3\]~105COUT1 5 COMB LAB_X2_Y9 2 " "Info: 5: + IC(0.000 ns) + CELL(0.080 ns) = 1.285 ns; Loc. = LAB_X2_Y9; Fanout = 2; COMB Node = 'fifo_data\[3\]~105COUT1'" {  } { { "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "E:/code/EP1C6/T2_USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "E:/code/EP1C6/T2_USB_IN/Proj/" "" "0.080 ns" { fifo_data[2]~101COUT1_127 fifo_data[3]~105COUT1 } "NODE_NAME" } "" } } { "../Src/fpga2pc.v" "" { Text "E:/code/EP1C6/T2_USB_IN/Src/fpga2pc.v" 17 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.258 ns) 1.543 ns fifo_data\[4\]~109 6 COMB LAB_X2_Y9 3 " "Info: 6: + IC(0.000 ns) + CELL(0.258 ns) = 1.543 ns; Loc. = LAB_X2_Y9; Fanout = 3; COMB Node = 'fifo_data\[4\]~109'" {  } { { "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "E:/code/EP1C6/T2_USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "E:/code/EP1C6/T2_USB_IN/Proj/" "" "0.258 ns" { fifo_data[3]~105COUT1 fifo_data[4]~109 } "NODE_NAME" } "" } } { "../Src/fpga2pc.v" "" { Text "E:/code/EP1C6/T2_USB_IN/Src/fpga2pc.v" 17 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.898 ns) 2.441 ns fifo_data\[5\]~reg0 7 REG LAB_X2_Y9 4 " "Info: 7: + IC(0.000 ns) + CELL(0.898 ns) = 2.441 ns; Loc. = LAB_X2_Y9; Fanout = 4; REG Node = 'fifo_data\[5\]~reg0'" {  } { { "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "E:/code/EP1C6/T2_USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "E:/code/EP1C6/T2_USB_IN/Proj/" "" "0.898 ns" { fifo_data[4]~109 fifo_data[5]~reg0 } "NODE_NAME" } "" } } { "../Src/fpga2pc.v" "" { Text "E:/code/EP1C6/T2_USB_IN/Src/fpga2pc.v" 74 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.971 ns 80.75 % " "Info: Total cell delay = 1.971 ns ( 80.75 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.470 ns 19.25 % " "Info: Total interconnect delay = 0.470 ns ( 19.25 % )" {  } {  } 0}  } { { "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "E:/code/EP1C6/T2_USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "E:/code/EP1C6/T2_USB_IN/Proj/" "" "2.441 ns" { fifo_data[0]~reg0 fifo_data[0]~93COUT1_125 fifo_data[1]~97COUT1_126 fifo_data[2]~101COUT1_127 fifo_data[3]~105COUT1 fifo_data[4]~109 fifo_data[5]~reg0 } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 0 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%." {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Warning" "WFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "1 " "Warning: The following 1 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "fifo_rd VCC " "Info: Pin fifo_rd has VCC driving its datain port" {  } { { "../Src/fpga2pc.v" "" { Text "E:/code/EP1C6/T2_USB_IN/Src/fpga2pc.v" 19 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "fifo_rd" } } } } { "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "E:/code/EP1C6/T2_USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "E:/code/EP1C6/T2_USB_IN/Proj/" "" "" { fifo_rd } "NODE_NAME" } "" } } { "E:/code/EP1C6/T2_USB_IN/Proj/fpga2pc.fld" "" { Floorplan "E:/code/EP1C6/T2_USB_IN/Proj/fpga2pc.fld" "" "" { fifo_rd } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Feb 23 15:01:19 2006 " "Info: Processing ended: Thu Feb 23 15:01:19 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0}  } {  } 0}