fpga2pc.tan.qmsg

来自「我买的红色飓风FPGA,EP1C6开发板的配套USBA实验例程 use输入模块的」· QMSG 代码 · 共 11 行 · 第 1/3 页

{ "Info" "ITDB_TH_RESULT" "STATE.WRITE_1 fifo_full clk 1.212 ns register " "Info: th for register \"STATE.WRITE_1\" (data pin = \"fifo_full\", clock pin = \"clk\") is 1.212 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 9.191 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 9.191 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_153 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 1; CLK Node = 'clk'" {  } { { "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "E:/code/EP1C6/T2_USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "E:/code/EP1C6/T2_USB_IN/Proj/" "" "" { clk } "NODE_NAME" } "" } } { "../Src/fpga2pc.v" "" { Text "E:/code/EP1C6/T2_USB_IN/Src/fpga2pc.v" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.587 ns) + CELL(0.935 ns) 3.991 ns clkin 2 REG LC_X19_Y10_N2 13 " "Info: 2: + IC(1.587 ns) + CELL(0.935 ns) = 3.991 ns; Loc. = LC_X19_Y10_N2; Fanout = 13; REG Node = 'clkin'" {  } { { "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "E:/code/EP1C6/T2_USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "E:/code/EP1C6/T2_USB_IN/Proj/" "" "2.522 ns" { clk clkin } "NODE_NAME" } "" } } { "../Src/fpga2pc.v" "" { Text "E:/code/EP1C6/T2_USB_IN/Src/fpga2pc.v" 32 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.489 ns) + CELL(0.711 ns) 9.191 ns STATE.WRITE_1 3 REG LC_X2_Y9_N8 5 " "Info: 3: + IC(4.489 ns) + CELL(0.711 ns) = 9.191 ns; Loc. = LC_X2_Y9_N8; Fanout = 5; REG Node = 'STATE.WRITE_1'" {  } { { "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "E:/code/EP1C6/T2_USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "E:/code/EP1C6/T2_USB_IN/Proj/" "" "5.200 ns" { clkin STATE.WRITE_1 } "NODE_NAME" } "" } } { "../Src/fpga2pc.v" "" { Text "E:/code/EP1C6/T2_USB_IN/Src/fpga2pc.v" 33 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns 33.89 % " "Info: Total cell delay = 3.115 ns ( 33.89 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.076 ns 66.11 % " "Info: Total interconnect delay = 6.076 ns ( 66.11 % )" {  } {  } 0}  } { { "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "E:/code/EP1C6/T2_USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "E:/code/EP1C6/T2_USB_IN/Proj/" "" "9.191 ns" { clk clkin STATE.WRITE_1 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "9.191 ns" { clk clk~out0 clkin STATE.WRITE_1 } { 0.000ns 0.000ns 1.587ns 4.489ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "../Src/fpga2pc.v" "" { Text "E:/code/EP1C6/T2_USB_IN/Src/fpga2pc.v" 33 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.994 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.994 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns fifo_full 1 PIN PIN_54 3 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_54; Fanout = 3; PIN Node = 'fifo_full'" {  } { { "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "E:/code/EP1C6/T2_USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "E:/code/EP1C6/T2_USB_IN/Proj/" "" "" { fifo_full } "NODE_NAME" } "" } } { "../Src/fpga2pc.v" "" { Text "E:/code/EP1C6/T2_USB_IN/Src/fpga2pc.v" 15 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.787 ns) + CELL(0.738 ns) 7.994 ns STATE.WRITE_1 2 REG LC_X2_Y9_N8 5 " "Info: 2: + IC(5.787 ns) + CELL(0.738 ns) = 7.994 ns; Loc. = LC_X2_Y9_N8; Fanout = 5; REG Node = 'STATE.WRITE_1'" {  } { { "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "E:/code/EP1C6/T2_USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "E:/code/EP1C6/T2_USB_IN/Proj/" "" "6.525 ns" { fifo_full STATE.WRITE_1 } "NODE_NAME" } "" } } { "../Src/fpga2pc.v" "" { Text "E:/code/EP1C6/T2_USB_IN/Src/fpga2pc.v" 33 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.207 ns 27.61 % " "Info: Total cell delay = 2.207 ns ( 27.61 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.787 ns 72.39 % " "Info: Total interconnect delay = 5.787 ns ( 72.39 % )" {  } {  } 0}  } { { "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "E:/code/EP1C6/T2_USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "E:/code/EP1C6/T2_USB_IN/Proj/" "" "7.994 ns" { fifo_full STATE.WRITE_1 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.994 ns" { fifo_full fifo_full~out0 STATE.WRITE_1 } { 0.000ns 0.000ns 5.787ns } { 0.000ns 1.469ns 0.738ns } } }  } 0}  } { { "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "E:/code/EP1C6/T2_USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "E:/code/EP1C6/T2_USB_IN/Proj/" "" "9.191 ns" { clk clkin STATE.WRITE_1 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "9.191 ns" { clk clk~out0 clkin STATE.WRITE_1 } { 0.000ns 0.000ns 1.587ns 4.489ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" "" { Report "E:/code/EP1C6/T2_USB_IN/Proj/db/fpga2pc_cmp.qrpt" Compiler "fpga2pc" "UNKNOWN" "V1" "E:/code/EP1C6/T2_USB_IN/Proj/db/USB_IN.quartus_db" { Floorplan "E:/code/EP1C6/T2_USB_IN/Proj/" "" "7.994 ns" { fifo_full STATE.WRITE_1 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.994 ns" { fifo_full fifo_full~out0 STATE.WRITE_1 } { 0.000ns 0.000ns 5.787ns } { 0.000ns 1.469ns 0.738ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Feb 23 15:01:25 2006 " "Info: Processing ended: Thu Feb 23 15:01:25 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}